[PATCH] D107692: [DAGCombine] Prevent the transform of combine for multi-use operand

[Allen zhong via Phabricator via llvm-commits]

Allen marked 2 inline comments as done.
Allen added a comment.

this patch is expected to fix the runtime bug, and more cases to be optimized can be consider in another  issue :)

When we use w8 replace the w1 , then the following two fragment codes is not equal.
so if the  SimplifyDemandedBits does the same transform, a patch can be land separate to fix this firstly to avoid the runtime bug.

  sub w8, w0, #1
  and w0, w8, w8, lsr #16

vs.

  mov w8, #65535
  add w8, w0, w8
  and w0, w8, w8, lsr #16



================
Comment at: llvm/test/CodeGen/AArch64/arm64-srl-and.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=tsv110 -O3 < %s | FileCheck %s
+
----------------
dmgreen wrote:
> This needs a triple, and likely doesn't need a -mcpu.
thanks, done


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107692/new/

https://reviews.llvm.org/D107692