[PATCH] D107657: [RISCV][VP] Add support for VP_REDUCE_* operations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:2055
+// Promote either the vector operand of a VECREDUCE_* or VP_REDUCE_* node, or
+// the start value of a VP_REDUCE node.
+SDValue DAGTypeLegalizer::PromoteIntOp_VEC_VP_REDUCE(SDNode *N, unsigned OpNo) {
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frasercrmck wrote:
> craig.topper wrote:
> > Are we allowing the start value to have a different type than the result? Or should we make them them same and handle start promotion when we handle result promotion. I think that would also mean we need to insert an appropriate extend if promoting the vector forces the result type to be enlarged?
> I think it's probably best if we say that the start and result should have the same type. I can see that promoting the start value when promoting the result value is nice and consistent in that regard. Is that something that's typically done?
> 
> And yes I think you're right about also extending the start value in the case that the vector is promoted.
> I think it's probably best if we say that the start and result should have the same type. I can see that promoting the start value when promoting the result value is nice and consistent in that regard. Is that something that's typically done?

Yes. If you do them at the same time then there is no transient state where they have a different type. We could even assert it in getNode we want.

> 
> And yes I think you're right about also extending the start value in the case that the vector is promoted.




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https://reviews.llvm.org/D107657