[PATCH] D106408: Allow rematerialization of virtual reg uses

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:123-125
+  /// in the function. If \p AllowVRegs is set to true then virtual register
+  /// uses are allowed as well for regalloc to opportunistically rematerialize
+  /// an instruction if all used registers happen to be available.
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arsenm wrote:
> rampitec wrote:
> > arsenm wrote:
> > > arsenm wrote:
> > > > I don't understand why AllowVRegs needs to be a parameter. Why wouldn't it just always true?
> > > i.e. this is rematerializable, the pressure question is a different heuristic
> > The problem is licm will hoist instructions if rematerializable even without checking the pressure (not saying its pressure calculation is not great) simply because if we run out of registers it will be easy to rematerialize the instruction. This is not the case with vreg uses, even if possible RA will not do it if it needs extending LR. The rematerialization in RA is opportunistic and not granted. Besides it is not even always possible to rematerialize such instructions even with all checks passed.
> But why can't licm check if there are vregs on the instruction itself? Why thread this through the legality check?
A good idea, thanks! I can do it as a separate patch preceding this one and instead of D107677.


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  https://reviews.llvm.org/D106408/new/

https://reviews.llvm.org/D106408