[PATCH] D107692: [DAGCombine] Prevent the transform of combine for multi-use operand

[Allen zhong via Phabricator via llvm-commits]

Allen added a comment.

In D107692#2932650 <https://reviews.llvm.org/D107692#2932650>, @lebedev.ri wrote:

> 1. Please upload all patches with full context. (`-U99999`)
> 2. I do not understand how one-use check here is acting as a correctness check

sorry for late reply, but I think you already know. as the node t46 has multi use, so `add t45, 65535` to `sub t45, -1` is not save in this case.

t64: i32 = srl t46, Constant:i64<16>

    t14: i32 = and t46, t64
  t46: i32 = add t45, Constant:i32<65535>



================
Comment at: llvm/test/CodeGen/AArch64/arm64-srl-and.ll:11
+; CHECK-NEXT:    add w8, w8, w9
+; CHECK-NEXT:    and w0, w8, w8, lsr #16
+entry:
----------------
dmgreen wrote:
> Has this deleted some of the check lines?
yes, as others are not the kernel code about this issue.


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https://reviews.llvm.org/D107692