[PATCH] D96075: [PowerPC] Exploit Prefixed Load/Stores using the refactored Load/Store Implementation

[Amy Kwan via Phabricator via llvm-commits]

amyk updated this revision to Diff 364999.
amyk added a comment.

Discussed offline with Nemanja to update the revision.

- Add assert for the paired vector intrinsics
- Add assert for 256-bit vectors

I've also changed `PPCRegisterInfo.cpp` to take prefixed instructions into account.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96075/new/

https://reviews.llvm.org/D96075

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
  llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
  llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
  llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
  llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
  llvm/test/CodeGen/PowerPC/f128_ldst.ll
  llvm/test/CodeGen/PowerPC/int128_ldst.ll
  llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/p10-fi-elim.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
  llvm/test/CodeGen/PowerPC/pcrel_ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-double-ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-float-ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-i64-ldst.ll
  llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
  llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
  llvm/test/CodeGen/PowerPC/vector-ldst.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D96075.364999.patch
Type: text/x-patch
Size: 217898 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210808/3f003864/attachment-0001.bin>