[llvm] 657bb72 - [M68k] Separate ADDA from ADD and migrate rest of the arithmetic MC tests

Min-Yih Hsu via llvm-commits llvm-commits at lists.llvm.org
Sat Aug 7 17:19:38 PDT 2021


Author: Min-Yih Hsu
Date: 2021-08-07T17:19:12-07:00
New Revision: 657bb7262d4a53e903e702d46fdcab57b7085128

URL: https://github.com/llvm/llvm-project/commit/657bb7262d4a53e903e702d46fdcab57b7085128
DIFF: https://github.com/llvm/llvm-project/commit/657bb7262d4a53e903e702d46fdcab57b7085128.diff

LOG: [M68k] Separate ADDA from ADD and migrate rest of the arithmetic MC tests

Previously ADD & ADDA (as well as SUB & SUBA) instructions are mixed
together, which not only violated Motorola assembly's syntax but also
made asm parsing more difficult. This patch separates these two kinds of
instructions migrate rest of the tests from
test/CodeGen/M68k/Encoding/Arithmetic to test/MC/M68k/Arithmetic.

Note that we observed minor regressions on codegen quality: Sometimes
isel uses ADD instead of ADDA even the latter can lead to shorter
sequence of code. This issue implies that some isel patterns might need
to be updated.

Added: 
    llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRI_xEA.s
    llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRM.s
    llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRR_xEA.s
    llvm/test/MC/M68k/Arith/Classes/MxCMP_BI.s
    llvm/test/MC/M68k/Arith/Classes/MxCMP_MI.s
    llvm/test/MC/M68k/Arith/Classes/MxCMP_RM.s

Modified: 
    llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
    llvm/lib/Target/M68k/M68kFrameLowering.cpp
    llvm/lib/Target/M68k/M68kInstrArithmetic.td
    llvm/lib/Target/M68k/M68kInstrCompiler.td
    llvm/lib/Target/M68k/M68kInstrFormats.td
    llvm/lib/Target/M68k/M68kInstrInfo.h
    llvm/lib/Target/M68k/M68kInstrInfo.td
    llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll
    llvm/test/CodeGen/M68k/Arith/add.ll
    llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
    llvm/test/CodeGen/M68k/Arith/imul.ll
    llvm/test/CodeGen/M68k/Arith/mul64.ll
    llvm/test/CodeGen/M68k/Arith/sdiv-exact.ll
    llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
    llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
    llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
    llvm/test/CodeGen/M68k/CConv/c-call.ll
    llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
    llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll
    llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
    llvm/test/CodeGen/M68k/CodeModel/medium-pie.ll
    llvm/test/CodeGen/M68k/CodeModel/medium-static.ll
    llvm/test/CodeGen/M68k/CodeModel/small-pic.ll
    llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
    llvm/test/CodeGen/M68k/CodeModel/small-pie.ll
    llvm/test/CodeGen/M68k/CodeModel/small-static.ll
    llvm/test/CodeGen/M68k/Control/cmp.ll
    llvm/test/CodeGen/M68k/Control/setcc.ll
    llvm/test/CodeGen/M68k/Encoding/Control/branch-pc-rel.mir
    llvm/test/CodeGen/M68k/Encoding/Relaxations/branch.mir
    llvm/test/CodeGen/M68k/inline-asm.ll
    llvm/test/CodeGen/M68k/varargs.ll
    llvm/test/MC/M68k/instructions.s

Removed: 
    llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRI_xEA.mir
    llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRM.mir
    llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRR_xEA.mir
    llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_BI.mir
    llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_MI.mir
    llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_RM.mir


################################################################################
diff  --git a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
index d8465f6d682b7..e9ce3892dba53 100644
--- a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+++ b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
@@ -149,8 +149,16 @@ class M68kOperand : public MCParsedAsmOperand {
 
   // Reg
   bool isReg() const override;
+  bool isAReg() const;
+  bool isDReg() const;
   unsigned getReg() const override;
   void addRegOperands(MCInst &Inst, unsigned N) const;
+  void addARegOperands(MCInst &Inst, unsigned N) const {
+    addRegOperands(Inst, N);
+  }
+  void addDRegOperands(MCInst &Inst, unsigned N) const {
+    addRegOperands(Inst, N);
+  }
 
   static std::unique_ptr<M68kOperand> createMemOp(M68kMemOp MemOp, SMLoc Start,
                                                   SMLoc End);
@@ -412,6 +420,18 @@ static inline bool checkRegisterClass(unsigned RegNo, bool Data, bool Address,
   }
 }
 
+bool M68kOperand::isAReg() const {
+  return isReg() && checkRegisterClass(getReg(),
+                                       /*Data=*/false,
+                                       /*Address=*/true, /*SP=*/true);
+}
+
+bool M68kOperand::isDReg() const {
+  return isReg() && checkRegisterClass(getReg(),
+                                       /*Data=*/true,
+                                       /*Address=*/false, /*SP=*/false);
+}
+
 unsigned M68kAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
                                                    unsigned Kind) {
   M68kOperand &Operand = (M68kOperand &)Op;

diff  --git a/llvm/lib/Target/M68k/M68kFrameLowering.cpp b/llvm/lib/Target/M68k/M68kFrameLowering.cpp
index 26262b9b573de..66ea6ae38f430 100644
--- a/llvm/lib/Target/M68k/M68kFrameLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kFrameLowering.cpp
@@ -357,7 +357,7 @@ void M68kFrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
       if (Reg) {
         unsigned Opc = M68k::MOV32ri;
         BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg).addImm(Offset);
-        Opc = IsSub ? M68k::SUB32rr : M68k::ADD32rr;
+        Opc = IsSub ? M68k::SUB32ar : M68k::ADD32ar;
         MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
                                .addReg(StackPtr)
                                .addReg(Reg);
@@ -400,13 +400,13 @@ int M68kFrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
     return Offset;
   }
 
-  if (Opc == M68k::ADD32ri && PI->getOperand(0).getReg() == StackPtr) {
+  if (Opc == M68k::ADD32ai && PI->getOperand(0).getReg() == StackPtr) {
     assert(PI->getOperand(1).getReg() == StackPtr);
     Offset += PI->getOperand(2).getImm();
     MBB.erase(PI);
     if (!MergeWithPrevious)
       MBBI = NI;
-  } else if (Opc == M68k::SUB32ri && PI->getOperand(0).getReg() == StackPtr) {
+  } else if (Opc == M68k::SUB32ai && PI->getOperand(0).getReg() == StackPtr) {
     assert(PI->getOperand(1).getReg() == StackPtr);
     Offset -= PI->getOperand(2).getImm();
     MBB.erase(PI);
@@ -426,7 +426,7 @@ MachineInstrBuilder M68kFrameLowering::BuildStackAdjustment(
 
   bool IsSub = Offset < 0;
   uint64_t AbsOffset = IsSub ? -Offset : Offset;
-  unsigned Opc = IsSub ? M68k::SUB32ri : M68k::ADD32ri;
+  unsigned Opc = IsSub ? M68k::SUB32ai : M68k::ADD32ai;
 
   MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
                                .addReg(StackPtr)

diff  --git a/llvm/lib/Target/M68k/M68kInstrArithmetic.td b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
index f65ad5729eb49..b2c05365d30b7 100644
--- a/llvm/lib/Target/M68k/M68kInstrArithmetic.td
+++ b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
@@ -88,14 +88,15 @@ let Defs = [CCR] in {
 let Constraints = "$src = $dst" in {
 
 // $reg, $ccr <- $reg op $reg
-class MxBiArOp_RFRR_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD, MxBead REG>
-    : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
-             MN#"."#TYPE.Prefix#"\t$opd, $dst",
-             [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
+class MxBiArOp_RFRR_xEA<string MN, SDNode NODE, MxType DST_TYPE, MxType SRC_TYPE,
+                        bits<4> CMD, MxBead REG>
+    : MxInst<(outs DST_TYPE.ROp:$dst), (ins DST_TYPE.ROp:$src, SRC_TYPE.ROp:$opd),
+             MN#"."#DST_TYPE.Prefix#"\t$opd, $dst",
+             [(set DST_TYPE.VT:$dst, CCR, (NODE DST_TYPE.VT:$src, SRC_TYPE.VT:$opd))],
              MxArithEncoding<MxBead4Bits<CMD>,
-                             !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
+                             !cast<MxEncOpMode>("MxOpMode"#DST_TYPE.Size#DST_TYPE.RLet#"EA"),
                              REG,
-                             !cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_2"),
+                             !cast<MxEncEA>("MxEncEA"#SRC_TYPE.RLet#"_2"),
                              MxExtEmpty>>;
 
 /// This Op is similar to the one above except it uses reversed opmode, some
@@ -260,11 +261,19 @@ multiclass MxBiArOp_DF<string MN, SDNode NODE, bit isComm,
   def NAME#"32ji" : MxBiArOp_FMI<MN, NODE, MxType32, MxType32.JOp, MxType32.JPat,
                                  CMDI, MxEncEAj_0, MxExtEmpty>;
 
+  def NAME#"16dr" : MxBiArOp_RFRR_xEA<MN, NODE, MxType16d, MxType16r,
+                                      CMD, MxBeadDReg<0>>;
+  def NAME#"32dr" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32d, MxType32r,
+                                      CMD, MxBeadDReg<0>>;
+
   let isCommutable = isComm in {
 
-    def NAME#"8dd"  : MxBiArOp_RFRR_xEA<MN, NODE, MxType8d,  CMD, MxBeadDReg<0>>;
-    def NAME#"16dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType16d, CMD, MxBeadDReg<0>>;
-    def NAME#"32dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32d, CMD, MxBeadDReg<0>>;
+    def NAME#"8dd"  : MxBiArOp_RFRR_xEA<MN, NODE, MxType8d, MxType8d,
+                                        CMD, MxBeadDReg<0>>;
+    def NAME#"16dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType16d, MxType16d,
+                                        CMD, MxBeadDReg<0>>;
+    def NAME#"32dd" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32d, MxType32d,
+                                        CMD, MxBeadDReg<0>>;
 
   } // isComm
 
@@ -278,29 +287,29 @@ let Pattern = [(null_frag)] in
 multiclass MxBiArOp_AF<string MN, SDNode NODE, bit isComm,
                        bits<4> CMD, bits<4> CMDI> {
 
-  def NAME#"32rk" : MxBiArOp_RFRM<MN, NODE, MxType32r, MxType32.KOp, MxType32.KPat,
+  def NAME#"32ak" : MxBiArOp_RFRM<MN, NODE, MxType32a, MxType32.KOp, MxType32.KPat,
                                   CMD, MxEncEAk, MxExtBrief_2>;
-  def NAME#"32rq" : MxBiArOp_RFRM<MN, NODE, MxType32r, MxType32.QOp, MxType32.QPat,
+  def NAME#"32aq" : MxBiArOp_RFRM<MN, NODE, MxType32a, MxType32.QOp, MxType32.QPat,
                                   CMD, MxEncEAq, MxExtI16_2>;
-  def NAME#"32rf" : MxBiArOp_RFRM<MN, NODE, MxType32r, MxType32.FOp, MxType32.FPat,
+  def NAME#"32af" : MxBiArOp_RFRM<MN, NODE, MxType32a, MxType32.FOp, MxType32.FPat,
                                   CMD, MxEncEAf_2, MxExtBrief_2>;
-  def NAME#"32rp" : MxBiArOp_RFRM<MN, NODE, MxType32r, MxType32.POp, MxType32.PPat,
+  def NAME#"32ap" : MxBiArOp_RFRM<MN, NODE, MxType32a, MxType32.POp, MxType32.PPat,
                                   CMD, MxEncEAp_2, MxExtI16_2>;
-  def NAME#"32rj" : MxBiArOp_RFRM<MN, NODE, MxType32r, MxType32.JOp, MxType32.JPat,
+  def NAME#"32aj" : MxBiArOp_RFRM<MN, NODE, MxType32a, MxType32.JOp, MxType32.JPat,
                                   CMD, MxEncEAj_2, MxExtEmpty>;
-  def NAME#"32ri" : MxBiArOp_RFRI_xEA<MN, NODE, MxType32r, CMD>;
+  def NAME#"32ai" : MxBiArOp_RFRI_xEA<MN, NODE, MxType32a, CMD>;
 
-  let isCommutable = isComm in
-  def NAME#"32rr" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32r, CMD, MxBeadReg<0>>;
+  def NAME#"32ar" : MxBiArOp_RFRR_xEA<MN, NODE, MxType32a, MxType32r,
+                                      CMD, MxBeadReg<0>>;
 
 } // MxBiArOp_AF
 
 // NOTE These naturally produce CCR
 
-defm ADD : MxBiArOp_DF<"add", MxAdd, 1, 0xD, 0x6>;
-defm ADD : MxBiArOp_AF<"add", MxAdd, 1, 0xD, 0x6>;
-defm SUB : MxBiArOp_DF<"sub", MxSub, 0, 0x9, 0x4>;
-defm SUB : MxBiArOp_AF<"sub", MxSub, 0, 0x9, 0x4>;
+defm ADD : MxBiArOp_DF<"add",  MxAdd, 1, 0xD, 0x6>;
+defm ADD : MxBiArOp_AF<"adda", MxAdd, 1, 0xD, 0x6>;
+defm SUB : MxBiArOp_DF<"sub",  MxSub, 0, 0x9, 0x4>;
+defm SUB : MxBiArOp_AF<"suba", MxSub, 0, 0x9, 0x4>;
 
 
 let Uses = [CCR], Defs = [CCR] in {
@@ -366,13 +375,16 @@ defm XOR : MxBiArOp_DF_EAd<"eor", MxXor, 0xB, 0xA>;
 //===----------------------------------------------------------------------===//
 
 let Defs = [CCR] in {
-class MxCmp_RR<MxType TYPE>
-    : MxInst<(outs), (ins TYPE.ROp:$lhs, TYPE.ROp:$rhs),
-             "cmp."#TYPE.Prefix#"\t$lhs, $rhs",
-             [(set CCR, (MxCmp TYPE.VT:$lhs, TYPE.VT:$rhs))],
+class MxCmp_RR<MxType LHS_TYPE, MxType RHS_TYPE = LHS_TYPE,
+               MxBead REG = MxBeadDReg<1>>
+    : MxInst<(outs), (ins LHS_TYPE.ROp:$lhs, RHS_TYPE.ROp:$rhs),
+             "cmp."#RHS_TYPE.Prefix#"\t$lhs, $rhs",
+             [(set CCR, (MxCmp LHS_TYPE.VT:$lhs, RHS_TYPE.VT:$rhs))],
              MxArithEncoding<MxBead4Bits<0xB>,
-                             !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"dEA"),
-                             MxBeadDReg<1>, MxEncEAd_0, MxExtEmpty>>;
+                             !cast<MxEncOpMode>("MxOpMode"#RHS_TYPE.Size#RHS_TYPE.RLet#"EA"),
+                             REG,
+                             !cast<MxEncEA>("MxEncEA"#LHS_TYPE.RLet#"_0"),
+                             MxExtEmpty>>;
 
 class MxCmp_RI<MxType TYPE>
     : MxInst<(outs), (ins TYPE.IOp:$imm, TYPE.ROp:$reg),
@@ -444,11 +456,16 @@ multiclass MMxCmp_MI<MxType TYPE> {
 }
 
 foreach S = [8, 16, 32] in {
-  def CMP#S#dd : MxCmp_RR<!cast<MxType>("MxType"#S#"d")>;
   def CMP#S#di : MxCmp_RI<!cast<MxType>("MxType"#S#"d")>;
   def CMP#S#bi : MxCmp_BI<!cast<MxType>("MxType"#S#"d")>;
 } // foreach
 
+def CMP8dd : MxCmp_RR<MxType8d>;
+foreach S = [16, 32] in {
+  def CMP#S#dr : MxCmp_RR<!cast<MxType>("MxType"#S#"r"),
+                          !cast<MxType>("MxType"#S#"d")>;
+}
+
 // cmp mem, Dn
 defm CMP8d  : MMxCmp_RM<MxType8d>;
 defm CMP16d : MMxCmp_RM<MxType16d>;
@@ -737,9 +754,9 @@ foreach N = ["add", "addc"] in {
   def : Pat<(!cast<SDNode>(N) i8 :$src, i8 :$opd),
             (ADD8dd  MxDRD8 :$src, MxDRD8 :$opd)>;
   def : Pat<(!cast<SDNode>(N) i16:$src, i16:$opd),
-            (ADD16dd MxDRD16:$src, MxDRD16:$opd)>;
+            (ADD16dr MxXRD16:$src, MxDRD16:$opd)>;
   def : Pat<(!cast<SDNode>(N) i32:$src, i32:$opd),
-            (ADD32rr MxXRD32:$src, MxXRD32:$opd)>;
+            (ADD32dr MxXRD32:$src, MxDRD32:$opd)>;
 
   // add (An), reg
   def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.JPat:$opd)),
@@ -747,7 +764,7 @@ foreach N = ["add", "addc"] in {
   def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.JPat:$opd)),
             (ADD16dj MxDRD16:$src, MxType16.JOp:$opd)>;
   def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.JPat:$opd)),
-            (ADD32rj MxXRD32:$src, MxType32.JOp:$opd)>;
+            (ADD32dj MxDRD32:$src, MxType32.JOp:$opd)>;
 
   // add (i,An), reg
   def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.PPat:$opd)),
@@ -755,7 +772,7 @@ foreach N = ["add", "addc"] in {
   def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.PPat:$opd)),
             (ADD16dp MxDRD16:$src, MxType16.POp:$opd)>;
   def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.PPat:$opd)),
-            (ADD32rp MxXRD32:$src, MxType32.POp:$opd)>;
+            (ADD32dp MxDRD32:$src, MxType32.POp:$opd)>;
 
   // add (i,An,Xn), reg
   def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.FPat:$opd)),
@@ -763,7 +780,7 @@ foreach N = ["add", "addc"] in {
   def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.FPat:$opd)),
             (ADD16df MxDRD16:$src, MxType16.FOp:$opd)>;
   def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.FPat:$opd)),
-            (ADD32rf MxXRD32:$src, MxType32.FOp:$opd)>;
+            (ADD32df MxDRD32:$src, MxType32.FOp:$opd)>;
 
   // add reg, imm
   def : Pat<(!cast<SDNode>(N) i8: $src, MximmSExt8:$opd),
@@ -776,7 +793,7 @@ foreach N = ["add", "addc"] in {
   // we make sure it will be selected over LEAp
   let AddedComplexity = 15 in {
   def : Pat<(!cast<SDNode>(N) i32:$src, MximmSExt32:$opd),
-            (ADD32ri MxXRD32:$src, imm:$opd)>;
+            (ADD32di MxDRD32:$src, imm:$opd)>;
   } // AddedComplexity = 15
 
   // add imm, (An)
@@ -806,7 +823,7 @@ foreach N = ["sub", "subc"] in {
   def : Pat<(!cast<SDNode>(N) i16:$src, i16:$opd),
             (SUB16dd MxDRD16:$src, MxDRD16:$opd)>;
   def : Pat<(!cast<SDNode>(N) i32:$src, i32:$opd),
-            (SUB32rr MxXRD32:$src, MxXRD32:$opd)>;
+            (SUB32dd MxDRD32:$src, MxDRD32:$opd)>;
 
 
   // sub (An), reg
@@ -815,7 +832,7 @@ foreach N = ["sub", "subc"] in {
   def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.JPat:$opd)),
             (SUB16dj MxDRD16:$src, MxType16.JOp:$opd)>;
   def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.JPat:$opd)),
-            (SUB32rj MxXRD32:$src, MxType32.JOp:$opd)>;
+            (SUB32dj MxDRD32:$src, MxType32.JOp:$opd)>;
 
   // sub (i,An), reg
   def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.PPat:$opd)),
@@ -823,7 +840,7 @@ foreach N = ["sub", "subc"] in {
   def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.PPat:$opd)),
             (SUB16dp MxDRD16:$src, MxType16.POp:$opd)>;
   def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.PPat:$opd)),
-            (SUB32rp MxXRD32:$src, MxType32.POp:$opd)>;
+            (SUB32dp MxDRD32:$src, MxType32.POp:$opd)>;
 
   // sub (i,An,Xn), reg
   def : Pat<(!cast<SDNode>(N) MxType8.VT:$src, (Mxloadi8 MxType8.FPat:$opd)),
@@ -831,7 +848,7 @@ foreach N = ["sub", "subc"] in {
   def : Pat<(!cast<SDNode>(N) MxType16.VT:$src, (Mxloadi16 MxType16.FPat:$opd)),
             (SUB16df MxDRD16:$src, MxType16.FOp:$opd)>;
   def : Pat<(!cast<SDNode>(N) MxType32.VT:$src, (Mxloadi32 MxType32.FPat:$opd)),
-            (SUB32rf MxXRD32:$src, MxType32.FOp:$opd)>;
+            (SUB32df MxDRD32:$src, MxType32.FOp:$opd)>;
 
   // sub reg, imm
   def : Pat<(!cast<SDNode>(N) i8 :$src, MximmSExt8 :$opd),
@@ -839,7 +856,7 @@ foreach N = ["sub", "subc"] in {
   def : Pat<(!cast<SDNode>(N) i16:$src, MximmSExt16:$opd),
             (SUB16di MxDRD16:$src, imm:$opd)>;
   def : Pat<(!cast<SDNode>(N) i32:$src, MximmSExt32:$opd),
-            (SUB32ri MxXRD32:$src, imm:$opd)>;
+            (SUB32di MxDRD32:$src, imm:$opd)>;
 
   // sub imm, (An)
   def : Pat<(store (!cast<SDNode>(N) (load MxType8.JPat:$dst), MxType8.IPat:$opd),

diff  --git a/llvm/lib/Target/M68k/M68kInstrCompiler.td b/llvm/lib/Target/M68k/M68kInstrCompiler.td
index bcb815dbc4ebf..8fb331dec0e9c 100644
--- a/llvm/lib/Target/M68k/M68kInstrCompiler.td
+++ b/llvm/lib/Target/M68k/M68kInstrCompiler.td
@@ -23,15 +23,15 @@ def : Pat<(i32 (MxWrapper tjumptable    :$src)), (MOV32ri tjumptable    :$src)>;
 def : Pat<(i32 (MxWrapper tblockaddress :$src)), (MOV32ri tblockaddress :$src)>;
 
 def : Pat<(add MxDRD32:$src, (MxWrapper tconstpool:$opd)),
-          (ADD32ri MxDRD32:$src, tconstpool:$opd)>;
+          (ADD32di MxDRD32:$src, tconstpool:$opd)>;
 def : Pat<(add MxARD32:$src, (MxWrapper tjumptable:$opd)),
-          (ADD32ri MxARD32:$src, tjumptable:$opd)>;
+          (ADD32ai MxARD32:$src, tjumptable:$opd)>;
 def : Pat<(add MxARD32:$src, (MxWrapper tglobaladdr :$opd)),
-          (ADD32ri MxARD32:$src, tglobaladdr:$opd)>;
+          (ADD32ai MxARD32:$src, tglobaladdr:$opd)>;
 def : Pat<(add MxARD32:$src, (MxWrapper texternalsym:$opd)),
-          (ADD32ri MxARD32:$src, texternalsym:$opd)>;
+          (ADD32ai MxARD32:$src, texternalsym:$opd)>;
 def : Pat<(add MxARD32:$src, (MxWrapper tblockaddress:$opd)),
-          (ADD32ri MxARD32:$src, tblockaddress:$opd)>;
+          (ADD32ai MxARD32:$src, tblockaddress:$opd)>;
 
 def : Pat<(store (i32 (MxWrapper tglobaladdr:$src)), iPTR:$dst),
           (MOV32ji MxARI32:$dst, tglobaladdr:$src)>;

diff  --git a/llvm/lib/Target/M68k/M68kInstrFormats.td b/llvm/lib/Target/M68k/M68kInstrFormats.td
index 1d950bd0377ae..99b7ffd17971d 100644
--- a/llvm/lib/Target/M68k/M68kInstrFormats.td
+++ b/llvm/lib/Target/M68k/M68kInstrFormats.td
@@ -250,7 +250,7 @@ def MxOpMode16dEA : MxEncOpMode<MxBead3Bits<0b001>>;
 def MxOpMode32dEA : MxEncOpMode<MxBead3Bits<0b010>>;
 
 // op EA, An
-def MxOpMode16aEA : MxEncOpMode<MxBead3Bits<0b110>>;
+def MxOpMode16aEA : MxEncOpMode<MxBead3Bits<0b011>>;
 def MxOpMode32aEA : MxEncOpMode<MxBead3Bits<0b111>>;
 
 // op EA, Rn

diff  --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h
index a503b02c5a825..6aced14873650 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.h
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.h
@@ -173,7 +173,7 @@ static inline unsigned IsCMP(unsigned Op) {
   case M68k::CMP8di:
   case M68k::CMP8dj:
   case M68k::CMP8dp:
-  case M68k::CMP16dd:
+  case M68k::CMP16dr:
   case M68k::CMP16df:
   case M68k::CMP16di:
   case M68k::CMP16dj:

diff  --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index e743213830de8..e465f256c097b 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -171,6 +171,13 @@ class MxOpClass<string name> : AsmOperandClass {
 }
 
 def MxRegClass : MxOpClass<"Reg">;
+// Splitting asm register class to avoid ambiguous on operands'
+// MatchClassKind. For instance, without this separation,
+// both ADD32dd and ADD32dr has {MCK_RegClass, MCK_RegClass} for
+// their operands, which makes AsmParser unable to pick the correct
+// one in a deterministic way.
+def MxARegClass : MxOpClass<"AReg">;
+def MxDRegClass : MxOpClass<"DReg">;
 
 class MxOperand<ValueType vt, MxSize size, string letter, RegisterClass rc, dag pat = (null_frag)> {
   ValueType VT = vt;
@@ -200,20 +207,24 @@ def MxXRD32_TC : MxRegOp<i32, XR32_TC, MxSize32, "r">;
 
 // DATA REGISTER DIRECT. The operand is in the data register specified by
 // the effective address register field.
-def MxDRD8  : MxRegOp<i8,  DR8,  MxSize8,  "d">;
-def MxDRD16 : MxRegOp<i16, DR16, MxSize16, "d">;
-def MxDRD32 : MxRegOp<i32, DR32, MxSize32, "d">;
+let ParserMatchClass = MxDRegClass in {
+  def MxDRD8  : MxRegOp<i8,  DR8,  MxSize8,  "d">;
+  def MxDRD16 : MxRegOp<i16, DR16, MxSize16, "d">;
+  def MxDRD32 : MxRegOp<i32, DR32, MxSize32, "d">;
 
-def MxDRD16_TC : MxRegOp<i16, DR16_TC, MxSize16, "d">;
-def MxDRD32_TC : MxRegOp<i32, DR32_TC, MxSize32, "d">;
+  def MxDRD16_TC : MxRegOp<i16, DR16_TC, MxSize16, "d">;
+  def MxDRD32_TC : MxRegOp<i32, DR32_TC, MxSize32, "d">;
+}
 
 // ADDRESS REGISTER DIRECT. The operand is in the address register specified by
 // the effective address register field.
-def MxARD16 : MxRegOp<i16, AR16, MxSize16, "a">;
-def MxARD32 : MxRegOp<i32, AR32, MxSize32, "a">;
+let ParserMatchClass = MxARegClass in {
+  def MxARD16 : MxRegOp<i16, AR16, MxSize16, "a">;
+  def MxARD32 : MxRegOp<i32, AR32, MxSize32, "a">;
 
-def MxARD16_TC : MxRegOp<i16, AR16_TC, MxSize16, "a">;
-def MxARD32_TC : MxRegOp<i32, AR32_TC, MxSize32, "a">;
+  def MxARD16_TC : MxRegOp<i16, AR16_TC, MxSize16, "a">;
+  def MxARD32_TC : MxRegOp<i32, AR32_TC, MxSize32, "a">;
+}
 
 class MxMemOp<dag ops, MxSize size, string letter,
               string printMethod = "printOperand",

diff  --git a/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll b/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll
index 7b0724c2f69a2..b3d8f8d3b66d2 100644
--- a/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll
+++ b/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll
@@ -12,7 +12,7 @@ define i32 @A(i32 %Size) {
 ; CHECK-NEXT:    move.l %sp, %d0
 ; CHECK-NEXT:    and.l #-128, %d0
 ; CHECK-NEXT:    move.l %d0, %sp
-; CHECK-NEXT:    sub.l #128, %sp
+; CHECK-NEXT:    suba.l #128, %sp
 ; CHECK-NEXT:    move.l %sp, %a4
 ; CHECK-NEXT:    movem.l %a4, (116,%a4) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.l (8,%a6), %d1

diff  --git a/llvm/test/CodeGen/M68k/Arith/add.ll b/llvm/test/CodeGen/M68k/Arith/add.ll
index 75c560f9b4b03..19d8d619083c9 100644
--- a/llvm/test/CodeGen/M68k/Arith/add.ll
+++ b/llvm/test/CodeGen/M68k/Arith/add.ll
@@ -40,7 +40,7 @@ define fastcc void @test2_fast(i32* inreg %a) nounwind {
 define fastcc void @test3(i64* inreg %a) nounwind {
 ; CHECK-LABEL: test3:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.l (%a0), %d0
 ; CHECK-NEXT:    move.l #0, %d1
@@ -50,7 +50,7 @@ define fastcc void @test3(i64* inreg %a) nounwind {
 ; CHECK-NEXT:    move.l %d2, (4,%a0)
 ; CHECK-NEXT:    move.l %d1, (%a0)
 ; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
   %aa = load i64, i64* %a
   %b = add i64 %aa, 2147483648
@@ -61,7 +61,7 @@ define fastcc void @test3(i64* inreg %a) nounwind {
 define fastcc void @test4(i64* inreg %a) nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.l (%a0), %d0
 ; CHECK-NEXT:    move.l #0, %d1
@@ -71,7 +71,7 @@ define fastcc void @test4(i64* inreg %a) nounwind {
 ; CHECK-NEXT:    move.l %d2, (4,%a0)
 ; CHECK-NEXT:    move.l %d1, (%a0)
 ; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
   %aa = load i64, i64* %a
   %b = add i64 %aa, 128

diff  --git a/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll b/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
index b695202f8ec2e..4711ff6e648a3 100644
--- a/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
+++ b/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
@@ -53,7 +53,7 @@ entry:
 define signext i16 @test4(i16 signext %x) nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.w (10,%sp), %d0
 ; CHECK-NEXT:    muls #1986, %d0
@@ -62,11 +62,10 @@ define signext i16 @test4(i16 signext %x) nounwind {
 ; CHECK-NEXT:    move.w #15, %d1
 ; CHECK-NEXT:    move.w %d0, %d2
 ; CHECK-NEXT:    lsr.w %d1, %d2
-; CHECK-NEXT:    add.w %d0, %d2
-; CHECK-NEXT:    move.l %d2, %d0
+; CHECK-NEXT:    add.w %d2, %d0
 ; CHECK-NEXT:    ext.l %d0
 ; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
 	%div = sdiv i16 %x, 33		; <i32> [#uses=1]
@@ -76,11 +75,11 @@ entry:
 define i32 @test5(i32 %A) nounwind {
 ; CHECK-LABEL: test5:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.l #12, %sp
+; CHECK-NEXT:    suba.l #12, %sp
 ; CHECK-NEXT:    move.l #1577682821, (4,%sp)
 ; CHECK-NEXT:    move.l (16,%sp), (%sp)
-; CHECK-NEXT:    jsr __udivsi3
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    jsr __udivsi3 at PLT
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
   %tmp1 = udiv i32 %A, 1577682821         ; <i32> [#uses=1]
   ret i32 %tmp1
@@ -90,7 +89,7 @@ define i32 @test5(i32 %A) nounwind {
 define signext i16 @test6(i16 signext %x) nounwind {
 ; CHECK-LABEL: test6:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.w (10,%sp), %d0
 ; CHECK-NEXT:    muls #26215, %d0
@@ -103,7 +102,7 @@ define signext i16 @test6(i16 signext %x) nounwind {
 ; CHECK-NEXT:    add.w %d2, %d0
 ; CHECK-NEXT:    ext.l %d0
 ; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
   %div = sdiv i16 %x, 10
@@ -113,11 +112,11 @@ entry:
 define i32 @test7(i32 %x) nounwind {
 ; CHECK-LABEL: test7:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.l #12, %sp
+; CHECK-NEXT:    suba.l #12, %sp
 ; CHECK-NEXT:    move.l #28, (4,%sp)
 ; CHECK-NEXT:    move.l (16,%sp), (%sp)
-; CHECK-NEXT:    jsr __udivsi3
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    jsr __udivsi3 at PLT
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
   %div = udiv i32 %x, 28
   ret i32 %div
@@ -157,18 +156,18 @@ define i8 @test9(i8 %x) nounwind {
 define i32 @testsize1(i32 %x) minsize nounwind {
 ; CHECK-LABEL: testsize1:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.l #31, %d1
-; CHECK-NEXT:    move.l (8,%sp), %d2
-; CHECK-NEXT:    move.l %d2, %d0
-; CHECK-NEXT:    asr.l %d1, %d0
+; CHECK-NEXT:    move.l (8,%sp), %d0
+; CHECK-NEXT:    move.l %d0, %d2
+; CHECK-NEXT:    asr.l %d1, %d2
 ; CHECK-NEXT:    move.l #27, %d1
-; CHECK-NEXT:    lsr.l %d1, %d0
+; CHECK-NEXT:    lsr.l %d1, %d2
 ; CHECK-NEXT:    add.l %d2, %d0
 ; CHECK-NEXT:    asr.l #5, %d0
 ; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
 	%div = sdiv i32 %x, 32
@@ -178,11 +177,11 @@ entry:
 define i32 @testsize2(i32 %x) minsize nounwind {
 ; CHECK-LABEL: testsize2:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #12, %sp
+; CHECK-NEXT:    suba.l #12, %sp
 ; CHECK-NEXT:    move.l #33, (4,%sp)
 ; CHECK-NEXT:    move.l (16,%sp), (%sp)
-; CHECK-NEXT:    jsr __divsi3
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    jsr __divsi3 at PLT
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
 entry:
 	%div = sdiv i32 %x, 33
@@ -203,11 +202,11 @@ entry:
 define i32 @testsize4(i32 %x) minsize nounwind {
 ; CHECK-LABEL: testsize4:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #12, %sp
+; CHECK-NEXT:    suba.l #12, %sp
 ; CHECK-NEXT:    move.l #33, (4,%sp)
 ; CHECK-NEXT:    move.l (16,%sp), (%sp)
-; CHECK-NEXT:    jsr __udivsi3
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    jsr __udivsi3 at PLT
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
 entry:
 	%div = udiv i32 %x, 33

diff  --git a/llvm/test/CodeGen/M68k/Arith/imul.ll b/llvm/test/CodeGen/M68k/Arith/imul.ll
index 2ded4c6eb9359..f53568395c29b 100644
--- a/llvm/test/CodeGen/M68k/Arith/imul.ll
+++ b/llvm/test/CodeGen/M68k/Arith/imul.ll
@@ -16,7 +16,7 @@ define i64 @mul4_64(i64 %A) {
 ; CHECK-LABEL: mul4_64:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.l #30, %d0
@@ -28,7 +28,7 @@ define i64 @mul4_64(i64 %A) {
 ; CHECK-NEXT:    or.l %d2, %d0
 ; CHECK-NEXT:    lsl.l #2, %d1
 ; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
     %mul = mul i64 %A, 4
     ret i64 %mul
@@ -50,7 +50,7 @@ define i64 @mul4096_64(i64 %A) {
 ; CHECK-LABEL: mul4096_64:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #8, %sp
+; CHECK-NEXT:    suba.l #8, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -12
 ; CHECK-NEXT:    movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill
 ; CHECK-NEXT:    move.l #20, %d0
@@ -63,7 +63,7 @@ define i64 @mul4096_64(i64 %A) {
 ; CHECK-NEXT:    or.l %d2, %d0
 ; CHECK-NEXT:    lsl.l %d3, %d1
 ; CHECK-NEXT:    movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
-; CHECK-NEXT:    add.l #8, %sp
+; CHECK-NEXT:    adda.l #8, %sp
 ; CHECK-NEXT:    rts
     %mul = mul i64 %A, 4096
     ret i64 %mul
@@ -86,7 +86,7 @@ define i64 @mulmin4096_64(i64 %A) {
 ; CHECK-LABEL: mulmin4096_64:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #8, %sp
+; CHECK-NEXT:    suba.l #8, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -12
 ; CHECK-NEXT:    movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill
 ; CHECK-NEXT:    move.l #20, %d0
@@ -101,7 +101,7 @@ define i64 @mulmin4096_64(i64 %A) {
 ; CHECK-NEXT:    neg.l %d1
 ; CHECK-NEXT:    negx.l %d0
 ; CHECK-NEXT:    movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
-; CHECK-NEXT:    add.l #8, %sp
+; CHECK-NEXT:    adda.l #8, %sp
 ; CHECK-NEXT:    rts
     %mul = mul i64 %A, -4096
     ret i64 %mul
@@ -112,12 +112,12 @@ define i32 @mul_32(i32 %a, i32 %b) {
 ; CHECK-LABEL: mul_32:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #12, %sp
+; CHECK-NEXT:    suba.l #12, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -16
 ; CHECK-NEXT:    move.l (20,%sp), (4,%sp)
 ; CHECK-NEXT:    move.l (16,%sp), (%sp)
-; CHECK-NEXT:    jsr __mulsi3
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    jsr __mulsi3 at PLT
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
     %mul = mul i32 %a, %b
     ret i32 %mul
@@ -156,14 +156,14 @@ define i64 @mul_64(i64 %a, i64 %b) {
 ; CHECK-LABEL: mul_64:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #20, %sp
+; CHECK-NEXT:    suba.l #20, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -24
 ; CHECK-NEXT:    move.l (36,%sp), (12,%sp)
 ; CHECK-NEXT:    move.l (32,%sp), (8,%sp)
 ; CHECK-NEXT:    move.l (28,%sp), (4,%sp)
 ; CHECK-NEXT:    move.l (24,%sp), (%sp)
-; CHECK-NEXT:    jsr __muldi3
-; CHECK-NEXT:    add.l #20, %sp
+; CHECK-NEXT:    jsr __muldi3 at PLT
+; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
     %mul = mul i64 %a, %b
     ret i64 %mul
@@ -173,14 +173,14 @@ define i64 @mul3_64(i64 %A) {
 ; CHECK-LABEL: mul3_64:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #20, %sp
+; CHECK-NEXT:    suba.l #20, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -24
 ; CHECK-NEXT:    move.l #3, (12,%sp)
 ; CHECK-NEXT:    move.l #0, (8,%sp)
 ; CHECK-NEXT:    move.l (28,%sp), (4,%sp)
 ; CHECK-NEXT:    move.l (24,%sp), (%sp)
-; CHECK-NEXT:    jsr __muldi3
-; CHECK-NEXT:    add.l #20, %sp
+; CHECK-NEXT:    jsr __muldi3 at PLT
+; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
     %mul = mul i64 %A, 3
     ret i64 %mul
@@ -190,14 +190,14 @@ define i64 @mul40_64(i64 %A) {
 ; CHECK-LABEL: mul40_64:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #20, %sp
+; CHECK-NEXT:    suba.l #20, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -24
 ; CHECK-NEXT:    move.l #40, (12,%sp)
 ; CHECK-NEXT:    move.l #0, (8,%sp)
 ; CHECK-NEXT:    move.l (28,%sp), (4,%sp)
 ; CHECK-NEXT:    move.l (24,%sp), (%sp)
-; CHECK-NEXT:    jsr __muldi3
-; CHECK-NEXT:    add.l #20, %sp
+; CHECK-NEXT:    jsr __muldi3 at PLT
+; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
     %mul = mul i64 %A, 40
     ret i64 %mul

diff  --git a/llvm/test/CodeGen/M68k/Arith/mul64.ll b/llvm/test/CodeGen/M68k/Arith/mul64.ll
index e21e17226a5d6..f6228d4c63475 100644
--- a/llvm/test/CodeGen/M68k/Arith/mul64.ll
+++ b/llvm/test/CodeGen/M68k/Arith/mul64.ll
@@ -6,13 +6,13 @@
 define i64 @foo(i64 %t, i64 %u) nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.l #20, %sp
+; CHECK-NEXT:    suba.l #20, %sp
 ; CHECK-NEXT:    move.l (36,%sp), (12,%sp)
 ; CHECK-NEXT:    move.l (32,%sp), (8,%sp)
 ; CHECK-NEXT:    move.l (28,%sp), (4,%sp)
 ; CHECK-NEXT:    move.l (24,%sp), (%sp)
-; CHECK-NEXT:    jsr __muldi3
-; CHECK-NEXT:    add.l #20, %sp
+; CHECK-NEXT:    jsr __muldi3 at PLT
+; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
   %k = mul i64 %t, %u
   ret i64 %k

diff  --git a/llvm/test/CodeGen/M68k/Arith/sdiv-exact.ll b/llvm/test/CodeGen/M68k/Arith/sdiv-exact.ll
index e7e83c898df7d..bb6b4acc034df 100644
--- a/llvm/test/CodeGen/M68k/Arith/sdiv-exact.ll
+++ b/llvm/test/CodeGen/M68k/Arith/sdiv-exact.ll
@@ -5,12 +5,12 @@ define i32 @test1(i32 %x) {
 ; CHECK-LABEL: test1:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #12, %sp
+; CHECK-NEXT:    suba.l #12, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -16
 ; CHECK-NEXT:    move.l #-1030792151, (4,%sp)
 ; CHECK-NEXT:    move.l (16,%sp), (%sp)
-; CHECK-NEXT:    jsr __mulsi3
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    jsr __mulsi3 at PLT
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
   %div = sdiv exact i32 %x, 25
   ret i32 %div
@@ -20,14 +20,14 @@ define i32 @test2(i32 %x) {
 ; CHECK-LABEL: test2:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #12, %sp
+; CHECK-NEXT:    suba.l #12, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -16
 ; CHECK-NEXT:    move.l (16,%sp), %d0
 ; CHECK-NEXT:    asr.l #3, %d0
 ; CHECK-NEXT:    move.l %d0, (%sp)
 ; CHECK-NEXT:    move.l #-1431655765, (4,%sp)
-; CHECK-NEXT:    jsr __mulsi3
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    jsr __mulsi3 at PLT
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
   %div = sdiv exact i32 %x, 24
   ret i32 %div

diff  --git a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
index d3f54dfb25854..1d3371cce833a 100644
--- a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
@@ -11,7 +11,7 @@ declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63)
 define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind {
 ; CHECK-LABEL: test1:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #28, %sp
+; CHECK-NEXT:    suba.l #28, %sp
 ; CHECK-NEXT:    movem.l %d2-%d3, (20,%sp) ; 12-byte Folded Spill
 ; CHECK-NEXT:    move.l %d1, (12,%sp)
 ; CHECK-NEXT:    move.l #31, %d2
@@ -20,7 +20,7 @@ define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind {
 ; CHECK-NEXT:    move.l %d0, (4,%sp)
 ; CHECK-NEXT:    asr.l %d2, %d0
 ; CHECK-NEXT:    move.l %d0, (%sp)
-; CHECK-NEXT:    jsr __muldi3
+; CHECK-NEXT:    jsr __muldi3 at PLT
 ; CHECK-NEXT:    move.l %d1, %d3
 ; CHECK-NEXT:    asr.l %d2, %d3
 ; CHECK-NEXT:    sub.l %d3, %d0
@@ -30,18 +30,18 @@ define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind {
 ; CHECK-NEXT:  ; %bb.2: ; %overflow
 ; CHECK-NEXT:    lea (no,%pc), %a0
 ; CHECK-NEXT:    move.l %a0, (%sp)
-; CHECK-NEXT:    jsr printf
+; CHECK-NEXT:    jsr printf at PLT
 ; CHECK-NEXT:    move.b #0, %d0
 ; CHECK-NEXT:    bra .LBB0_3
 ; CHECK-NEXT:  .LBB0_1: ; %normal
 ; CHECK-NEXT:    move.l %d1, (4,%sp)
 ; CHECK-NEXT:    lea (ok,%pc), %a0
 ; CHECK-NEXT:    move.l %a0, (%sp)
-; CHECK-NEXT:    jsr printf
+; CHECK-NEXT:    jsr printf at PLT
 ; CHECK-NEXT:    move.b #1, %d0
 ; CHECK-NEXT:  .LBB0_3: ; %overflow
 ; CHECK-NEXT:    movem.l (20,%sp), %d2-%d3 ; 12-byte Folded Reload
-; CHECK-NEXT:    add.l #28, %sp
+; CHECK-NEXT:    adda.l #28, %sp
 ; CHECK-NEXT:    rts
 entry:
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -61,7 +61,7 @@ overflow:
 define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #28, %sp
+; CHECK-NEXT:    suba.l #28, %sp
 ; CHECK-NEXT:    movem.l %d2-%d3, (20,%sp) ; 12-byte Folded Spill
 ; CHECK-NEXT:    move.l %d1, (12,%sp)
 ; CHECK-NEXT:    move.l #31, %d2
@@ -70,7 +70,7 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
 ; CHECK-NEXT:    move.l %d0, (4,%sp)
 ; CHECK-NEXT:    asr.l %d2, %d0
 ; CHECK-NEXT:    move.l %d0, (%sp)
-; CHECK-NEXT:    jsr __muldi3
+; CHECK-NEXT:    jsr __muldi3 at PLT
 ; CHECK-NEXT:    move.l %d1, %d3
 ; CHECK-NEXT:    asr.l %d2, %d3
 ; CHECK-NEXT:    sub.l %d3, %d0
@@ -80,18 +80,18 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
 ; CHECK-NEXT:  ; %bb.1: ; %overflow
 ; CHECK-NEXT:    lea (no,%pc), %a0
 ; CHECK-NEXT:    move.l %a0, (%sp)
-; CHECK-NEXT:    jsr printf
+; CHECK-NEXT:    jsr printf at PLT
 ; CHECK-NEXT:    move.b #0, %d0
 ; CHECK-NEXT:    bra .LBB1_2
 ; CHECK-NEXT:  .LBB1_3: ; %normal
 ; CHECK-NEXT:    move.l %d1, (4,%sp)
 ; CHECK-NEXT:    lea (ok,%pc), %a0
 ; CHECK-NEXT:    move.l %a0, (%sp)
-; CHECK-NEXT:    jsr printf
+; CHECK-NEXT:    jsr printf at PLT
 ; CHECK-NEXT:    move.b #1, %d0
 ; CHECK-NEXT:  .LBB1_2: ; %overflow
 ; CHECK-NEXT:    movem.l (20,%sp), %d2-%d3 ; 12-byte Folded Reload
-; CHECK-NEXT:    add.l #28, %sp
+; CHECK-NEXT:    adda.l #28, %sp
 ; CHECK-NEXT:    rts
 entry:
   %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)

diff  --git a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
index 5cd7458c357dc..da6d78a492882 100644
--- a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
@@ -11,24 +11,24 @@ declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32)
 define i1 @func1(i32 %v1, i32 %v2) nounwind {
 ; CHECK-LABEL: func1:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #12, %sp
+; CHECK-NEXT:    suba.l #12, %sp
 ; CHECK-NEXT:    move.l (16,%sp), %d0
 ; CHECK-NEXT:    sub.l (20,%sp), %d0
 ; CHECK-NEXT:    bvc .LBB0_1
 ; CHECK-NEXT:  ; %bb.2: ; %overflow
 ; CHECK-NEXT:    lea (no,%pc), %a0
 ; CHECK-NEXT:    move.l %a0, (%sp)
-; CHECK-NEXT:    jsr printf
+; CHECK-NEXT:    jsr printf at PLT
 ; CHECK-NEXT:    move.b #0, %d0
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
 ; CHECK-NEXT:  .LBB0_1: ; %normal
 ; CHECK-NEXT:    move.l %d0, (4,%sp)
 ; CHECK-NEXT:    lea (ok,%pc), %a0
 ; CHECK-NEXT:    move.l %a0, (%sp)
-; CHECK-NEXT:    jsr printf
+; CHECK-NEXT:    jsr printf at PLT
 ; CHECK-NEXT:    move.b #1, %d0
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
 entry:
   %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
@@ -48,24 +48,24 @@ overflow:
 define i1 @func2(i32 %v1, i32 %v2) nounwind {
 ; CHECK-LABEL: func2:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #12, %sp
+; CHECK-NEXT:    suba.l #12, %sp
 ; CHECK-NEXT:    move.l (16,%sp), %d0
 ; CHECK-NEXT:    sub.l (20,%sp), %d0
 ; CHECK-NEXT:    bcc .LBB1_1
 ; CHECK-NEXT:  ; %bb.2: ; %carry
 ; CHECK-NEXT:    lea (no,%pc), %a0
 ; CHECK-NEXT:    move.l %a0, (%sp)
-; CHECK-NEXT:    jsr printf
+; CHECK-NEXT:    jsr printf at PLT
 ; CHECK-NEXT:    move.b #0, %d0
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
 ; CHECK-NEXT:  .LBB1_1: ; %normal
 ; CHECK-NEXT:    move.l %d0, (4,%sp)
 ; CHECK-NEXT:    lea (ok,%pc), %a0
 ; CHECK-NEXT:    move.l %a0, (%sp)
-; CHECK-NEXT:    jsr printf
+; CHECK-NEXT:    jsr printf at PLT
 ; CHECK-NEXT:    move.b #1, %d0
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
 entry:
   %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)

diff  --git a/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
index 98f43e2a93855..df4e6417dc33a 100644
--- a/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
@@ -6,15 +6,15 @@ declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
 define i1 @a(i32 %x)  nounwind {
 ; CHECK-LABEL: a:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.l #20, %sp
+; CHECK-NEXT:    suba.l #20, %sp
 ; CHECK-NEXT:    move.l #3, (12,%sp)
 ; CHECK-NEXT:    move.l #0, (8,%sp)
 ; CHECK-NEXT:    move.l (24,%sp), (4,%sp)
 ; CHECK-NEXT:    move.l #0, (%sp)
-; CHECK-NEXT:    jsr __muldi3
+; CHECK-NEXT:    jsr __muldi3 at PLT
 ; CHECK-NEXT:    cmpi.l #0, %d0
 ; CHECK-NEXT:    sne %d0
-; CHECK-NEXT:    add.l #20, %sp
+; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
   %res = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 3)
   %obil = extractvalue {i32, i1} %res, 1

diff  --git a/llvm/test/CodeGen/M68k/CConv/c-call.ll b/llvm/test/CodeGen/M68k/CConv/c-call.ll
index a97f96c3ca904..a9638eec6a313 100644
--- a/llvm/test/CodeGen/M68k/CConv/c-call.ll
+++ b/llvm/test/CodeGen/M68k/CConv/c-call.ll
@@ -7,7 +7,7 @@
 define i32 @test1() nounwind {
 ; CHECK-LABEL: test1:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #20, %sp
+; CHECK-NEXT:    suba.l #20, %sp
 ; CHECK-NEXT:    move.l #5, (16,%sp)
 ; CHECK-NEXT:    move.l #4, (12,%sp)
 ; CHECK-NEXT:    move.l #3, (8,%sp)
@@ -15,7 +15,7 @@ define i32 @test1() nounwind {
 ; CHECK-NEXT:    move.l #1, (%sp)
 ; CHECK-NEXT:    jsr (test1_callee at PLT,%pc)
 ; CHECK-NEXT:    move.l #0, %d0
-; CHECK-NEXT:    add.l #20, %sp
+; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
 entry:
   call void @test1_callee(i32 1, i32 2, i32 3, i32 4, i32 5) nounwind
@@ -27,7 +27,7 @@ declare void @test1_callee(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e);
 define i16 @test2() nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #20, %sp
+; CHECK-NEXT:    suba.l #20, %sp
 ; CHECK-NEXT:    move.l #5, (16,%sp)
 ; CHECK-NEXT:    move.l #4, (12,%sp)
 ; CHECK-NEXT:    move.l #3, (8,%sp)
@@ -35,7 +35,7 @@ define i16 @test2() nounwind {
 ; CHECK-NEXT:    move.l #1, (%sp)
 ; CHECK-NEXT:    jsr (test2_callee at PLT,%pc)
 ; CHECK-NEXT:    move.w #0, %d0
-; CHECK-NEXT:    add.l #20, %sp
+; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
 entry:
   call void @test2_callee(i16 1, i16 2, i16 3, i16 4, i16 5) nounwind
@@ -47,7 +47,7 @@ declare void @test2_callee(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e);
 define i8 @test3() nounwind {
 ; CHECK-LABEL: test3:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #20, %sp
+; CHECK-NEXT:    suba.l #20, %sp
 ; CHECK-NEXT:    move.l #5, (16,%sp)
 ; CHECK-NEXT:    move.l #4, (12,%sp)
 ; CHECK-NEXT:    move.l #3, (8,%sp)
@@ -55,7 +55,7 @@ define i8 @test3() nounwind {
 ; CHECK-NEXT:    move.l #1, (%sp)
 ; CHECK-NEXT:    jsr (test3_callee at PLT,%pc)
 ; CHECK-NEXT:    move.b #0, %d0
-; CHECK-NEXT:    add.l #20, %sp
+; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
 entry:
   call void @test3_callee(i8 1, i8 2, i8 3, i8 4, i8 5) nounwind

diff  --git a/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll b/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
index 42f105cc6b080..5931f76d70b19 100644
--- a/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
+++ b/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
@@ -8,7 +8,7 @@ define i32 @foo1() nounwind uwtable {
 ; CHECK-LABEL: foo1:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    move.l #5, (%sp)
 ; CHECK-NEXT:    move.l #1, %d0
@@ -17,7 +17,7 @@ define i32 @foo1() nounwind uwtable {
 ; CHECK-NEXT:    move.l #4, %a1
 ; CHECK-NEXT:    jsr (bar1 at PLT,%pc)
 ; CHECK-NEXT:    move.l #0, %d0
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
   call fastcc void @bar1(i32 1, i32 2, i32 3, i32 4, i32 5) nounwind
@@ -31,7 +31,7 @@ define i32 @foo2() nounwind uwtable {
 ; CHECK-LABEL: foo2:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #12, %sp
+; CHECK-NEXT:    suba.l #12, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -16
 ; CHECK-NEXT:    lea (8,%sp), %a0
 ; CHECK-NEXT:    move.l #2, %d0
@@ -39,7 +39,7 @@ define i32 @foo2() nounwind uwtable {
 ; CHECK-NEXT:    move.l #4, %d1
 ; CHECK-NEXT:    jsr (bar2 at PLT,%pc)
 ; CHECK-NEXT:    move.l #0, %d0
-; CHECK-NEXT:    add.l #12, %sp
+; CHECK-NEXT:    adda.l #12, %sp
 ; CHECK-NEXT:    rts
 entry:
   %a = alloca i32, align 4

diff  --git a/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll
index 2a7cdea33bcb3..d4f607cc6435a 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll
@@ -48,10 +48,10 @@ declare i8* @malloc(i32)
 define void @test2() nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    move.l #40, (%sp)
 ; CHECK-NEXT:    jsr (malloc at PLT,%pc)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     %ptr = call i8* @malloc(i32 40)
@@ -64,13 +64,13 @@ declare void(...)* @afoo(...)
 define void @test3() nounwind {
 ; CHECK-LABEL: test3:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    jsr (afoo at PLT,%pc)
 ; CHECK-NEXT:    move.l %d0, %a0
 ; CHECK-NEXT:    move.l (pfoo at GOTPCREL,%pc), %a1
 ; CHECK-NEXT:    move.l %a0, (%a1)
 ; CHECK-NEXT:    jsr (%a0)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     %tmp = call void(...)*(...) @afoo()
@@ -85,9 +85,9 @@ declare void @foo(...)
 define void @test4() nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    jsr (foo at PLT,%pc)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     call void(...) @foo()
@@ -103,7 +103,7 @@ define void @test5() nounwind {
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    lea (_GLOBAL_OFFSET_TABLE_ at GOTPCREL,%pc), %a0
 ; CHECK-NEXT:    move.l %a0, %a1
-; CHECK-NEXT:    add.l #dst6 at GOTOFF, %a1
+; CHECK-NEXT:    adda.l #dst6 at GOTOFF, %a1
 ; CHECK-NEXT:    move.l #ptr6 at GOTOFF, %d0
 ; CHECK-NEXT:    move.l %a1, (0,%a0,%d0)
 ; CHECK-NEXT:    move.l #src6 at GOTOFF, %d0
@@ -129,8 +129,10 @@ define void @test7(i32 %n.u) nounwind {
 ; CHECK-NEXT:    lea (_GLOBAL_OFFSET_TABLE_ at GOTPCREL,%pc), %a0
 ; CHECK-NEXT:    lsl.l #2, %d0
 ; CHECK-NEXT:    move.l %a0, %a1
-; CHECK-NEXT:    add.l #.LJTI6_0 at GOTOFF, %a1
-; CHECK-NEXT:    add.l (0,%a1,%d0), %a0
+; CHECK-NEXT:    adda.l #.LJTI6_0 at GOTOFF, %a1
+; CHECK-NEXT:    move.l %a0, %d1
+; CHECK-NEXT:    add.l (0,%a1,%d0), %d1
+; CHECK-NEXT:    move.l %d1, %a0
 ; CHECK-NEXT:    jmp (%a0)
 ; CHECK-NEXT:  .LBB6_12: ; %bb2
 ; CHECK-NEXT:    bra foo6 at PLT ; TAILCALL

diff  --git a/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
index 38a65105ffaa6..00764582b603d 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
@@ -86,11 +86,11 @@ define i32 @my_access_fp_foo() #0 {
 ; CHECK-LABEL: my_access_fp_foo:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    move.l (foo at GOTPCREL,%pc), (%sp)
 ; CHECK-NEXT:    jsr (access_fp at PLT,%pc)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
  %call = call i32 @access_fp(i32 ()* @foo)
@@ -115,11 +115,11 @@ define i32 @my_access_fp_bar() #0 {
 ; CHECK-LABEL: my_access_fp_bar:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    move.l (bar at GOTPCREL,%pc), (%sp)
 ; CHECK-NEXT:    jsr (access_fp at PLT,%pc)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
  %call = call i32 @access_fp(i32 ()* @bar)

diff  --git a/llvm/test/CodeGen/M68k/CodeModel/medium-pie.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-pie.ll
index ee5301618cf47..bdae2a65e1c3a 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/medium-pie.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/medium-pie.ll
@@ -41,14 +41,14 @@ define void @bar() {
 ; CHECK-LABEL: bar:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    jsr (foo at PLT,%pc)
 ; CHECK-NEXT:    jsr (weak_odr_foo at PLT,%pc)
 ; CHECK-NEXT:    jsr (weak_foo at PLT,%pc)
 ; CHECK-NEXT:    jsr (internal_foo,%pc)
 ; CHECK-NEXT:    jsr (ext_baz at PLT,%pc)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
   call void @foo()

diff  --git a/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll
index 695fa94ca09bd..59480199b31e4 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll
@@ -42,10 +42,10 @@ declare i8* @malloc(i32)
 define void @test2() nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    move.l #40, (%sp)
 ; CHECK-NEXT:    jsr malloc at PLT
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     %ptr = call i8* @malloc(i32 40)
@@ -59,12 +59,12 @@ declare void(...)* @afoo(...)
 define void @test3() nounwind {
 ; CHECK-LABEL: test3:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    jsr afoo at PLT
 ; CHECK-NEXT:    move.l %d0, %a0
 ; CHECK-NEXT:    move.l %a0, pfoo
 ; CHECK-NEXT:    jsr (%a0)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     %tmp = call void(...)*(...) @afoo()
@@ -79,9 +79,9 @@ declare void @foo(...)
 define void @test4() nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    jsr foo at PLT
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     call void(...) @foo()

diff  --git a/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll b/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll
index a479abcdf57c0..d4256abb29b7a 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll
@@ -48,10 +48,10 @@ declare i8* @malloc(i32)
 define void @test2() nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    move.l #40, (%sp)
 ; CHECK-NEXT:    jsr (malloc at PLT,%pc)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     %ptr = call i8* @malloc(i32 40)
@@ -64,13 +64,13 @@ declare void(...)* @afoo(...)
 define void @test3() nounwind {
 ; CHECK-LABEL: test3:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    jsr (afoo at PLT,%pc)
 ; CHECK-NEXT:    move.l %d0, %a0
 ; CHECK-NEXT:    move.l (pfoo at GOTPCREL,%pc), %a1
 ; CHECK-NEXT:    move.l %a0, (%a1)
 ; CHECK-NEXT:    jsr (%a0)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     %tmp = call void(...)*(...) @afoo()
@@ -85,9 +85,9 @@ declare void @foo(...)
 define void @test4() nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    jsr (foo at PLT,%pc)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     call void(...) @foo()
@@ -124,7 +124,9 @@ define void @test7(i32 %n.u) nounwind {
 ; CHECK-NEXT:  ; %bb.1: ; %entry
 ; CHECK-NEXT:    lsl.l #2, %d0
 ; CHECK-NEXT:    lea (.LJTI6_0,%pc), %a0
-; CHECK-NEXT:    add.l (0,%a0,%d0), %a0
+; CHECK-NEXT:    move.l %a0, %d1
+; CHECK-NEXT:    add.l (0,%a0,%d0), %d1
+; CHECK-NEXT:    move.l %d1, %a0
 ; CHECK-NEXT:    jmp (%a0)
 ; CHECK-NEXT:  .LBB6_12: ; %bb2
 ; CHECK-NEXT:    bra foo6 at PLT ; TAILCALL

diff  --git a/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll b/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
index 21fc9676f1d0b..4d3ebf989ca99 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
@@ -84,11 +84,11 @@ define i32 @my_access_fp_foo() #0 {
 ; CHECK-LABEL: my_access_fp_foo:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    move.l (foo at GOTPCREL,%pc), (%sp)
 ; CHECK-NEXT:    jsr (access_fp at PLT,%pc)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
  %call = call i32 @access_fp(i32 ()* @foo)
@@ -113,11 +113,11 @@ define i32 @my_access_fp_bar() #0 {
 ; CHECK-LABEL: my_access_fp_bar:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    move.l (bar at GOTPCREL,%pc), (%sp)
 ; CHECK-NEXT:    jsr (access_fp at PLT,%pc)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
  %call = call i32 @access_fp(i32 ()* @bar)

diff  --git a/llvm/test/CodeGen/M68k/CodeModel/small-pie.ll b/llvm/test/CodeGen/M68k/CodeModel/small-pie.ll
index b1fc4ffb78a17..8d442d4c147b8 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/small-pie.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/small-pie.ll
@@ -42,14 +42,14 @@ define void @bar() {
 ; CHECK-LABEL: bar:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    jsr (foo at PLT,%pc)
 ; CHECK-NEXT:    jsr (weak_odr_foo at PLT,%pc)
 ; CHECK-NEXT:    jsr (weak_foo at PLT,%pc)
 ; CHECK-NEXT:    jsr (internal_foo,%pc)
 ; CHECK-NEXT:    jsr (ext_baz at PLT,%pc)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
   call void @foo()

diff  --git a/llvm/test/CodeGen/M68k/CodeModel/small-static.ll b/llvm/test/CodeGen/M68k/CodeModel/small-static.ll
index affbfc565321f..257d017623388 100644
--- a/llvm/test/CodeGen/M68k/CodeModel/small-static.ll
+++ b/llvm/test/CodeGen/M68k/CodeModel/small-static.ll
@@ -46,10 +46,10 @@ declare i8* @malloc(i32)
 define void @test2() nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    move.l #40, (%sp)
 ; CHECK-NEXT:    jsr malloc at PLT
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     %ptr = call i8* @malloc(i32 40)
@@ -62,13 +62,13 @@ declare void(...)* @afoo(...)
 define void @test3() nounwind {
 ; CHECK-LABEL: test3:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    jsr afoo at PLT
 ; CHECK-NEXT:    move.l %d0, %a0
 ; CHECK-NEXT:    lea (pfoo,%pc), %a1
 ; CHECK-NEXT:    move.l %a0, (%a1)
 ; CHECK-NEXT:    jsr (%a0)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     %tmp = call void(...)*(...) @afoo()
@@ -83,9 +83,9 @@ declare void @foo(...)
 define void @test4() nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    jsr foo at PLT
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
     call void(...) @foo()

diff  --git a/llvm/test/CodeGen/M68k/Control/cmp.ll b/llvm/test/CodeGen/M68k/Control/cmp.ll
index 122e514e9a7ac..46f981b4d1479 100644
--- a/llvm/test/CodeGen/M68k/Control/cmp.ll
+++ b/llvm/test/CodeGen/M68k/Control/cmp.ll
@@ -94,7 +94,7 @@ define i64 @test3(i64 %x) nounwind {
 define i64 @test4(i64 %x) nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.l (8,%sp), %d1
 ; CHECK-NEXT:    move.l #0, %d0
@@ -105,7 +105,7 @@ define i64 @test4(i64 %x) nounwind {
 ; CHECK-NEXT:    and.l #255, %d1
 ; CHECK-NEXT:    and.l #1, %d1
 ; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
   %t = icmp slt i64 %x, 1
   %r = zext i1 %t to i64
@@ -115,17 +115,17 @@ define i64 @test4(i64 %x) nounwind {
 define i32 @test6() nounwind align 2 {
 ; CHECK-LABEL: test6:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    sub.l #20, %sp
+; CHECK-NEXT:    suba.l #20, %sp
 ; CHECK-NEXT:    move.l (12,%sp), %d0
 ; CHECK-NEXT:    or.l (8,%sp), %d0
 ; CHECK-NEXT:    beq .LBB5_1
 ; CHECK-NEXT:  ; %bb.2: ; %F
 ; CHECK-NEXT:    move.l #0, %d0
-; CHECK-NEXT:    add.l #20, %sp
+; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
 ; CHECK-NEXT:  .LBB5_1: ; %T
 ; CHECK-NEXT:    move.l #1, %d0
-; CHECK-NEXT:    add.l #20, %sp
+; CHECK-NEXT:    adda.l #20, %sp
 ; CHECK-NEXT:    rts
   %A = alloca {i64, i64}, align 8
   %B = getelementptr inbounds {i64, i64}, {i64, i64}* %A, i64 0, i32 1
@@ -287,7 +287,7 @@ define void @test20(i32 %bf.load, i8 %x1, i8* %b_addr) {
 ; CHECK-LABEL: test20:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.l #16777215, %d0
@@ -297,13 +297,13 @@ define void @test20(i32 %bf.load, i8 %x1, i8* %b_addr) {
 ; CHECK-NEXT:    move.l (16,%sp), %a0
 ; CHECK-NEXT:    move.b (15,%sp), %d2
 ; CHECK-NEXT:    and.l #255, %d2
-; CHECK-NEXT:    add.l %d1, %d2
+; CHECK-NEXT:    add.l %d2, %d1
 ; CHECK-NEXT:    sne (%a0)
 ; CHECK-NEXT:    cmpi.l #0, %d0
 ; CHECK-NEXT:    lea (d,%pc), %a0
 ; CHECK-NEXT:    sne (%a0)
 ; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
   %bf.shl = shl i32 %bf.load, 8
   %bf.ashr = ashr exact i32 %bf.shl, 8

diff  --git a/llvm/test/CodeGen/M68k/Control/setcc.ll b/llvm/test/CodeGen/M68k/Control/setcc.ll
index 1e301bb1bda6d..f18a64d22ac3e 100644
--- a/llvm/test/CodeGen/M68k/Control/setcc.ll
+++ b/llvm/test/CodeGen/M68k/Control/setcc.ll
@@ -38,7 +38,7 @@ entry:
 define fastcc i64 @t3(i64 %x) nounwind readnone ssp {
 ; CHECK-LABEL: t3:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
 ; CHECK-NEXT:    move.l #0, %d2
 ; CHECK-NEXT:    sub.l #18, %d1
@@ -50,7 +50,7 @@ define fastcc i64 @t3(i64 %x) nounwind readnone ssp {
 ; CHECK-NEXT:    lsl.l #6, %d1
 ; CHECK-NEXT:    move.l %d2, %d0
 ; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
   %0 = icmp ult i64 %x, 18                        ; <i1> [#uses=1]

diff  --git a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRI_xEA.mir b/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRI_xEA.mir
deleted file mode 100644
index 09e06e0072b60..0000000000000
--- a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRI_xEA.mir
+++ /dev/null
@@ -1,45 +0,0 @@
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN:   | extract-section .text \
-# RUN:   | FileCheck %s -check-prefixes=ADD16DI,ADD32RI
-
-#------------------------------------------------------------------------------
-# MxBiArOp_RFRI_xEA class used for binary arithmetic operations and operates on
-# register and immediate data. It uses MxArithEncoding(yes for immediates) class
-# and either MxOpModeNdEA or MxOpmodeNrEA opmode classes.
-#------------------------------------------------------------------------------
-
-
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#                x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-# ADD16DI:       1   1   0   1   0   0   0   0 . 0   1   1   1   1   1   0   0
-# ADD16DI:       0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------+-----------+-----------+-----------+-----------
-# ADD16DI-SAME:  1   1   0   1   0   1   1   0 . 0   1   1   1   1   1   0   0
-# ADD16DI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-#               ---------------+-----------+-----------+-----------+-----------
-# ADD32RI-SAME:  1   1   0   1   0   0   0   0 . 1   0   1   1   1   1   0   0
-# ADD32RI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# ADD32RI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-#               ---------------+-----------+-----------+-----------+-----------
-# ADD32RI-SAME:  1   1   0   1   0   0   0   0 . 1   0   1   1   1   1   0   0
-# ADD32RI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   1
-# ADD32RI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-#               ---------------+-----------+-----------+-----------+-----------
-# ADD32RI-SAME:  1   1   0   1   1   1   1   0 . 1   0   1   1   1   1   0   0
-# ADD32RI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   1   1   1
-# ADD32RI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------+-----------+-----------+-----------+-----------
-# ADD32RI-SAME:  1   1   0   1   0   0   0   1 . 1   1   1   1   1   1   0   0
-# ADD32RI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# ADD32RI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-name: MxBiArOp_RFRI_xEA
-body: |
-  bb.0:
-    $wd0 = ADD16di $wd0, 0,      implicit-def $ccr
-    $wd3 = ADD16di $wd3, -1,     implicit-def $ccr
-    $d0  = ADD32ri  $d0, -1,     implicit-def $ccr
-    $d0  = ADD32ri  $d0, 131071, implicit-def $ccr
-    $d7  = ADD32ri  $d7, 458752, implicit-def $ccr
-    $a0  = ADD32ri  $a0, 0,      implicit-def $ccr

diff  --git a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRM.mir b/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRM.mir
deleted file mode 100644
index 28946f91bd365..0000000000000
--- a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRM.mir
+++ /dev/null
@@ -1,123 +0,0 @@
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN:   | extract-section .text \
-# RUN:   | FileCheck %s -check-prefixes=ADD8DK,ADD32RK,ADD8DQ,ADD32RQ,ADD8DF,ADD32RF
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN:   | extract-section .text \
-# RUN:   | FileCheck %s -check-prefixes=ADD8DP,ADD32RP,ADD8DJ,ADD32RJ
-
-#------------------------------------------------------------------------------
-# MxBiArOp_RFRM class used for binary arithmetic operations and operates on
-# register and memory. It uses MxArithEncoding encoding class and either
-# MxOpModeNdEA or MxOpModeNrEA opmode classes.
-#------------------------------------------------------------------------------
-
---- # PCI
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#       OPWORD   x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-#               ---------------+-----------+-----------+-----------+-----------
-# ADD8DK:        1   1   0   1   0   0   0   0 . 0   0   1   1   1   0   1   1
-# ADD8DK-SAME:   0   0   0   1   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# ADD8DK-SAME:   1   1   0   1   0   0   0   0 . 0   0   1   1   1   0   1   1
-# ADD8DK-SAME:   0   0   0   1   1   0   0   0 . 1   1   1   1   1   1   1   1
-#               ---------------------------------------------------------------
-# ADD32RK-SAME:  1   1   0   1   0   0   0   0 . 1   0   1   1   1   0   1   1
-# ADD32RK-SAME:  0   0   0   1   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# ADD32RK-SAME:  1   1   0   1   0   0   1   1 . 1   1   1   1   1   0   1   1
-# ADD32RK-SAME:  1   0   1   0   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---+-----------+---+-------+---+-------------------------------
-#        BRIEF  DA |    REG    | L | SCALE | 0 |          DISPLACEMENT
-#               ---+-----------+---+-------+---+-------------------------------
-name: MxBiArOp_RFRM_PCI
-body: |
-  bb.0:
-    $bd0 = ADD8dk $bd0, 0,  $d1, implicit-def $ccr
-    $bd0 = ADD8dk $bd0, -1, $d1, implicit-def $ccr
-    $d0  = ADD32rk $d0, 0,  $d1, implicit-def $ccr
-    $a1  = ADD32rk $a1, 0,  $a2, implicit-def $ccr
-
-...
---- # PCD
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#       OPWORD   x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-#               ---------------+-----------+-----------+-----------+-----------
-# ADD8DQ-SAME:   1   1   0   1   0   0   0   0 . 0   0   1   1   1   0   1   0
-# ADD8DQ-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# ADD32RQ-SAME:  1   1   0   1   0   0   0   0 . 1   0   1   1   1   0   1   0
-# ADD32RQ-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-name: MxBiArOp_RFRM_PCD
-body: |
-  bb.0:
-    $bd0 = ADD8dq $bd0, 0,  implicit-def $ccr
-    $d0  = ADD32rq $d0, -1, implicit-def $ccr
-
-...
---- # ARII
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#       OPWORD   x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-#               ---------------+-----------+-----------+-----------+-----------
-# ADD8DF-SAME:   1   1   0   1   0   0   0   0 . 0   0   1   1   0   0   0   0
-# ADD8DF-SAME:   0   0   0   1   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# ADD8DF-SAME:   1   1   0   1   0   0   0   0 . 0   0   1   1   0   0   0   0
-# ADD8DF-SAME:   0   0   0   1   1   0   0   0 . 1   1   1   1   1   1   1   1
-#               ---------------------------------------------------------------
-# ADD32RF-SAME:  1   1   0   1   0   0   0   0 . 1   0   1   1   0   0   0   1
-# ADD32RF-SAME:  0   0   0   1   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# ADD32RF-SAME:  1   1   0   1   0   0   1   1 . 1   1   1   1   0   0   1   0
-# ADD32RF-SAME:  1   0   1   0   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---+-----------+---+-------+---+-------------------------------
-#        BRIEF  DA |    REG    | L | SCALE | 0 |          DISPLACEMENT
-#               ---+-----------+---+-------+---+-------------------------------
-name: MxBiArOp_RFRM_ARII
-body: |
-  bb.0:
-    $bd0 = ADD8df $bd0, 0,  $a0, $d1, implicit-def $ccr
-    $bd0 = ADD8df $bd0, -1, $a0, $d1, implicit-def $ccr
-    $d0  = ADD32rf $d0, 0,  $a1, $d1, implicit-def $ccr
-    $a1  = ADD32rf $a1, 0,  $a2, $a2, implicit-def $ccr
-
-...
---- # ARID
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#       OPWORD   x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-#               ---------------+-----------+-----------+-----------+-----------
-# ADD8DP:        1   1   0   1   0   0   0   0 . 0   0   1   0   1   0   0   0
-# ADD8DP-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# ADD32RP-SAME:  1   1   0   1   0   0   0   0 . 1   0   1   0   1   0   0   1
-# ADD32RP-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-name: MxBiArOp_RFRM_ARID
-body: |
-  bb.0:
-    $bd0 = ADD8dp $bd0, 0,  $a0, implicit-def $ccr
-    $d0  = ADD32rp $d0, -1, $a1, implicit-def $ccr
-
-...
---- # ARI
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#       OPWORD   x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-#               ---------------+-----------+-----------+-----------+-----------
-# ADD8DJ-SAME:   1   1   0   1   0   0   0   0 . 0   0   0   1   0   0   0   0
-#               ---------------------------------------------------------------
-# ADD32RJ-SAME:  1   1   0   1   0   1   1   1 . 1   1   0   1   0   0   0   1
-name: MxBiArOp_RFRM_ARI
-body: |
-  bb.0:
-    $bd0 = ADD8dj $bd0, $a0, implicit-def $ccr
-    $a3  = ADD32rj $a3, $a1, implicit-def $ccr
-
-...

diff  --git a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRR_xEA.mir b/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRR_xEA.mir
deleted file mode 100644
index 41c49e71f761b..0000000000000
--- a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRR_xEA.mir
+++ /dev/null
@@ -1,30 +0,0 @@
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN:   | extract-section .text \
-# RUN:   | FileCheck %s -check-prefixes=ADD16DD,ADD32RR
-
-#------------------------------------------------------------------------------
-# MxBiArOp_RFRR_xEA class used for binary arithmetic operations and operates on
-# both data and address registers only. It uses MxArithEncoding encoding class
-# and either MxOpModeNdEA or MxOpmodeNrEA opmode classes.
-#------------------------------------------------------------------------------
-
-
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#                x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-# ADD16DD:       1   1   0   1   0   0   0   0 . 0   1   0   0   0   0   0   1
-# ADD16DD-SAME:  1   1   0   1   0   1   1   0 . 0   1   0   0   0   0   1   0
-# ADD32RR-SAME:  1   1   0   1   0   0   0   0 . 1   0   0   0   0   0   0   1
-# ADD32RR-SAME:  1   1   0   1   0   0   0   0 . 1   0   0   0   1   0   0   1
-# ADD32RR-SAME:  1   1   0   1   1   1   1   0 . 1   0   0   0   1   0   0   1
-# ADD32RR-SAME:  1   1   0   1   0   0   0   1 . 1   1   0   0   0   0   0   1
-name: MxBiArOp_RFRR_xEA
-body: |
-  bb.0:
-    $wd0 = ADD16dd $wd0, $wd1, implicit-def $ccr
-    $wd3 = ADD16dd $wd3, $wd2, implicit-def $ccr
-    $d0  = ADD32rr  $d0,  $d1, implicit-def $ccr
-    $d0  = ADD32rr  $d0,  $a1, implicit-def $ccr
-    $d7  = ADD32rr  $d7,  $a1, implicit-def $ccr
-    $a0  = ADD32rr  $a0,  $d1, implicit-def $ccr

diff  --git a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_BI.mir b/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_BI.mir
deleted file mode 100644
index 635bf44774511..0000000000000
--- a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_BI.mir
+++ /dev/null
@@ -1,44 +0,0 @@
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN:   | extract-section .text \
-# RUN:   | FileCheck %s -check-prefixes=CMP8BI,CMP32BI
-
-#------------------------------------------------------------------------------
-# MxCMP_BI class used for compare operations and operates on absolute memory
-# locations and immediate data. It uses MxArithImmEncoding encoding class.
-# NOTE: CMP is calculated by subtracting LHS(Imm) from RHS(ABS)
-#------------------------------------------------------------------------------
-
-
-#               -------------------------------+-------+-----------+-----------
-#                F   E   D   C   B   A   9   8 | 7   6 | 5   4   3 | 2   1   0
-#               -------------------------------+-------+-----------+-----------
-#       OPWORD   0   0   0   0   1   1   0   0 |  SIZE |    MODE   |    REG
-#               -------------------------------+-------+-----------+-----------
-# CMP8BI:        0   0   0   0   1   1   0   0 . 0   0   1   1   1   0   0   1
-# CMP8BI-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP8BI-SAME:   1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP8BI-SAME:   1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-#               -------------------------------+-------+-----------+-----------
-# CMP8BI-SAME:   0   0   0   0   1   1   0   0 . 0   0   1   1   1   0   0   1
-# CMP8BI-SAME:   0   0   0   0   0   0   0   0 . 1   1   1   1   1   1   1   1
-# CMP8BI-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP8BI-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP32BI-SAME:  0   0   0   0   1   1   0   0 . 1   0   1   1   1   0   0   1
-# CMP32BI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32BI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32BI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP32BI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP32BI-SAME:  0   0   0   0   1   1   0   0 . 1   0   1   1   1   0   0   1
-# CMP32BI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP32BI-SAME:  0   0   0   0   0   0   0   0 . 0   0   1   0   1   0   1   0
-# CMP32BI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32BI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-name: MxCMP_BI
-body: |
-  bb.0:
-    CMP8bi   0, -1, implicit-def $ccr
-    CMP8bi  -1,  0, implicit-def $ccr
-    CMP32bi -1,  0, implicit-def $ccr
-    CMP32bi 42, -1, implicit-def $ccr

diff  --git a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_MI.mir b/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_MI.mir
deleted file mode 100644
index 77037b22231a4..0000000000000
--- a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_MI.mir
+++ /dev/null
@@ -1,174 +0,0 @@
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN:   | extract-section .text \
-# RUN:   | FileCheck %s -check-prefixes=CMP8KI,CMP32KI,CMP8QI,CMP32QI,CMP8FI,CMP32FI
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN:   | extract-section .text \
-# RUN:   | FileCheck %s -check-prefixes=CMP8PI,CMP32PI,CMP8JI,CMP32JI
-
-#------------------------------------------------------------------------------
-# MxCMP_MI class used for compare operations and operates on memory data and
-# immediate data. It uses MxArithImmEncoding encoding class.
-# NOTE: CMP is calculated by subtracting LHS(Imm) from RHS(Mem)
-#------------------------------------------------------------------------------
-
-
---- # PCI
-#               -------------------------------+-------+-----------+-----------
-#                F   E   D   C   B   A   9   8 | 7   6 | 5   4   3 | 2   1   0
-#               -------------------------------+-------+-----------+-----------
-#       OPWORD   0   0   0   0   1   1   0   0 |  SIZE |    MODE   |    REG
-#               -------------------------------+-------+-----------+-----------
-# CMP8KI:        0   0   0   0   1   1   0   0 . 0   0   1   1   1   0   1   1
-# CMP8KI-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP8KI-SAME:   0   0   0   1   1   0   0   0 . 1   1   1   1   1   1   1   1
-#               -------------------------------+-------+-----------+-----------
-# CMP8KI-SAME:   0   0   0   0   1   1   0   0 . 0   0   1   1   1   0   1   1
-# CMP8KI-SAME:   0   0   0   0   0   0   0   0 . 1   1   1   1   1   1   1   1
-# CMP8KI-SAME:   0   0   0   0   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP32KI-SAME:  0   0   0   0   1   1   0   0 . 1   0   1   1   1   0   1   1
-# CMP32KI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32KI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32KI-SAME:  0   1   1   1   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP32KI-SAME:  0   0   0   0   1   1   0   0 . 1   0   1   1   1   0   1   1
-# CMP32KI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP32KI-SAME:  0   0   0   0   0   0   0   0 . 0   0   1   0   1   0   1   0
-# CMP32KI-SAME:  0   0   0   1   1   0   0   0 . 1   1   1   1   1   1   1   1
-#               ---+-----------+---+-------+---+-------------------------------
-#        BRIEF  DA |    REG    | L | SCALE | 0 |          DISPLACEMENT
-#               ---+-----------+---+-------+---+-------------------------------
-name: MxCMP_MI_PCI
-body: |
-  bb.0:
-    CMP8ki   0, -1, $d1, implicit-def $ccr
-    CMP8ki  -1,  0, $d0, implicit-def $ccr
-    CMP32ki -1,  0, $d7, implicit-def $ccr
-    CMP32ki 42, -1, $d1, implicit-def $ccr
-
-...
---- # PCD
-#               -------------------------------+-------+-----------+-----------
-#                F   E   D   C   B   A   9   8 | 7   6 | 5   4   3 | 2   1   0
-#               -------------------------------+-------+-----------+-----------
-#       OPWORD   0   0   0   0   1   1   0   0 |  SIZE |    MODE   |    REG
-#               -------------------------------+-------+-----------+-----------
-# CMP8QI-SAME:   0   0   0   0   1   1   0   0 . 0   0   1   1   1   0   1   0
-# CMP8QI-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP8QI-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP8QI-SAME:   0   0   0   0   1   1   0   0 . 0   0   1   1   1   0   1   0
-# CMP8QI-SAME:   0   0   0   0   0   0   0   0 . 1   1   1   1   1   1   1   1
-# CMP8QI-SAME:   1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-#               -------------------------------+-------+-----------+-----------
-# CMP32QI-SAME:  0   0   0   0   1   1   0   0 . 1   0   1   1   1   0   1   0
-# CMP32QI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32QI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32QI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP32QI-SAME:  0   0   0   0   1   1   0   0 . 1   0   1   1   1   0   1   0
-# CMP32QI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP32QI-SAME:  0   0   0   0   0   0   0   0 . 0   0   1   0   1   0   1   0
-# CMP32QI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-name: MxCMP_MI_PCD
-body: |
-  bb.0:
-    CMP8qi   0,  0, implicit-def $ccr
-    CMP8qi  -1, -1, implicit-def $ccr
-    CMP32qi -1,  0, implicit-def $ccr
-    CMP32qi 42,  0, implicit-def $ccr
-
-...
---- # ARII
-#               -------------------------------+-------+-----------+-----------
-#                F   E   D   C   B   A   9   8 | 7   6 | 5   4   3 | 2   1   0
-#               -------------------------------+-------+-----------+-----------
-#       OPWORD   0   0   0   0   1   1   0   0 |  SIZE |    MODE   |    REG
-#               -------------------------------+-------+-----------+-----------
-# CMP8FI-SAME:   0   0   0   0   1   1   0   0 . 0   0   1   1   0   0   0   1
-# CMP8FI-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP8FI-SAME:   1   0   0   0   1   0   0   0 . 1   1   1   1   1   1   1   1
-#               -------------------------------+-------+-----------+-----------
-# CMP8FI-SAME:   0   0   0   0   1   1   0   0 . 0   0   1   1   0   0   0   0
-# CMP8FI-SAME:   0   0   0   0   0   0   0   0 . 1   1   1   1   1   1   1   1
-# CMP8FI-SAME:   1   0   0   0   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP32FI-SAME:  0   0   0   0   1   1   0   0 . 1   0   1   1   0   1   1   0
-# CMP32FI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32FI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32FI-SAME:  1   0   0   0   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP32FI-SAME:  0   0   0   0   1   1   0   0 . 1   0   1   1   0   0   0   1
-# CMP32FI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP32FI-SAME:  0   0   0   0   0   0   0   0 . 0   0   1   0   1   0   1   0
-# CMP32FI-SAME:  1   0   0   0   1   0   0   0 . 1   1   1   1   1   1   1   1
-#               ---+-----------+---+-------+---+-------------------------------
-#        BRIEF  DA |    REG    | L | SCALE | 0 |          DISPLACEMENT
-#               ---+-----------+---+-------+---+-------------------------------
-name: MxCMP_MI_ARII
-body: |
-  bb.0:
-    CMP8fi   0, -1, $a1, $a0, implicit-def $ccr
-    CMP8fi  -1,  0, $a0, $a0, implicit-def $ccr
-    CMP32fi -1,  0, $a6, $a0, implicit-def $ccr
-    CMP32fi 42, -1, $a1, $a0, implicit-def $ccr
-
-...
---- # ARID
-#               -------------------------------+-------+-----------+-----------
-#                F   E   D   C   B   A   9   8 | 7   6 | 5   4   3 | 2   1   0
-#               -------------------------------+-------+-----------+-----------
-#       OPWORD   0   0   0   0   1   1   0   0 |  SIZE |    MODE   |    REG
-#               -------------------------------+-------+-----------+-----------
-# CMP8PI:        0   0   0   0   1   1   0   0 . 0   0   1   0   1   0   0   1
-# CMP8PI-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP8PI-SAME:   1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-#               -------------------------------+-------+-----------+-----------
-# CMP8PI-SAME:   0   0   0   0   1   1   0   0 . 0   0   1   0   1   0   0   0
-# CMP8PI-SAME:   0   0   0   0   0   0   0   0 . 1   1   1   1   1   1   1   1
-# CMP8PI-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP32PI-SAME:  0   0   0   0   1   1   0   0 . 1   0   1   0   1   1   1   0
-# CMP32PI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32PI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-# CMP32PI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP32PI-SAME:  0   0   0   0   1   1   0   0 . 1   0   1   0   1   0   0   1
-# CMP32PI-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-# CMP32PI-SAME:  0   0   0   0   0   0   0   0 . 0   0   1   0   1   0   1   0
-# CMP32PI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-name: MxCMP_MI_ARID
-body: |
-  bb.0:
-    CMP8pi   0, -1, $a1, implicit-def $ccr
-    CMP8pi  -1,  0, $a0, implicit-def $ccr
-    CMP32pi -1,  0, $a6, implicit-def $ccr
-    CMP32pi 42, -1, $a1, implicit-def $ccr
-
-...
---- # ARI
-#               -------------------------------+-------+-----------+-----------
-#                F   E   D   C   B   A   9   8 | 7   6 | 5   4   3 | 2   1   0
-#               -------------------------------+-------+-----------+-----------
-#       OPWORD   0   0   0   0   1   1   0   0 |  SIZE |    MODE   |    REG
-#               -------------------------------+-------+-----------+-----------
-# CMP8JI-SAME:   0   0   0   0   1   1   0   0 . 0   0   0   1   0   0   0   1
-# CMP8JI-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               -------------------------------+-------+-----------+-----------
-# CMP8JI-SAME:   0   0   0   0   1   1   0   0 . 0   0   0   1   0   0   0   0
-# CMP8JI-SAME:   0   0   0   0   0   0   0   0 . 1   1   1   1   1   1   1   1
-#               -------------------------------+-------+-----------+-----------
-# CMP32JI-SAME:  0   0   0   0   1   1   0   0 . 1   0   0   1   0   1   1   0
-# CMP32JI-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-#               -------------------------------+-------+-----------+-----------
-# CMP32JI-SAME:  0   0   0   0   1   1   0   0 . 1   0   0   1   0   0   0   1
-# CMP32JI-SAME:  0   0   0   0   0   0   0   0 . 0   0   1   0   1   0   1   0
-name: MxCMP_MI_ARI
-body: |
-  bb.0:
-    CMP8ji   0, $a1, implicit-def $ccr
-    CMP8ji  -1, $a0, implicit-def $ccr
-    CMP32ji -1, $a6, implicit-def $ccr
-    CMP32ji 42, $a1, implicit-def $ccr
-
-...

diff  --git a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_RM.mir b/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_RM.mir
deleted file mode 100644
index 27b13099c81d9..0000000000000
--- a/llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_RM.mir
+++ /dev/null
@@ -1,125 +0,0 @@
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN:   | extract-section .text \
-# RUN:   | FileCheck %s -check-prefixes=CMP8DF,CMP32DF
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN:   | extract-section .text \
-# RUN:   | FileCheck %s -check-prefixes=CMP8DP,CMP32DP,CMP8DJ,CMP32DJ
-
-#------------------------------------------------------------------------------
-# MxCMP_RM class used for compare operations and operates on memory data and
-# register. It uses MxArithEncoding encoding class.
-# NOTE: CMP is calculated by subtracting LHS(Mem) from RHS(Reg)
-#------------------------------------------------------------------------------
-
---- # PCI
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#       OPWORD   x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-#               ---------------+-----------+-----------+-----------+-----------
-# CMP8DK:        1   0   1   1   0   0   0   0 . 0   0   1   1   1   0   1   1
-# CMP8DK-SAME:   0   0   0   1   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# CMP8DK-SAME:   1   0   1   1   0   0   0   0 . 0   0   1   1   1   0   1   1
-# CMP8DK-SAME:   0   0   0   1   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# CMP32DK-SAME:  1   0   1   1   0   0   0   0 . 1   0   1   1   1   0   1   1
-# CMP32DK-SAME:  0   0   0   1   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---+-----------+---+-------+---+-------------------------------
-#        BRIEF  DA |    REG    | L | SCALE | 0 |          DISPLACEMENT
-#               ---+-----------+---+-------+---+-------------------------------
-#
-# NOTE Immediates for pc-rel instructions use relocations and addendum is encoded
-# inside the relocation record thus there are 0s instead of the value.
-name: MxBiArOp_RFRM_PCI
-body: |
-  bb.0:
-    CMP8dk  $bd0, 0,  $d1, implicit-def $ccr
-    CMP8dk  $bd0, -1, $d1, implicit-def $ccr
-    CMP32dk $d0, 0,  $d1, implicit-def $ccr
-
-...
---- # PCD
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#       OPWORD   x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-#               ---------------+-----------+-----------+-----------+-----------
-# CMP8DQ-SAME:   1   0   1   1   0   0   0   0 . 0   0   1   1   1   0   1   0
-# CMP8DQ-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# CMP32DQ-SAME:  1   0   1   1   0   0   0   0 . 1   0   1   1   1   0   1   0
-# CMP32DQ-SAME:  0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#
-# NOTE Immediates for pc-rel instructions use relocations and addendum is encoded
-# inside the relocation record thus there are 0s instead of the value.
-name: MxBiArOp_RFRM_PCD
-body: |
-  bb.0:
-    CMP8dq  $bd0, 0,  implicit-def $ccr
-    CMP32dq $d0, -1, implicit-def $ccr
-
-...
---- # ARII
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#       OPWORD   x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-#               ---------------+-----------+-----------+-----------+-----------
-# CMP8DF:        1   0   1   1   0   0   0   0 . 0   0   1   1   0   0   0   0
-# CMP8DF-SAME:   0   0   0   1   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# CMP8DF-SAME:   1   0   1   1   0   0   0   0 . 0   0   1   1   0   0   0   0
-# CMP8DF-SAME:   0   0   0   1   1   0   0   0 . 1   1   1   1   1   1   1   1
-#               ---------------------------------------------------------------
-# CMP32DF-SAME:  1   0   1   1   0   0   0   0 . 1   0   1   1   0   0   0   1
-# CMP32DF-SAME:  0   0   0   1   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# CMP32DF-SAME:  1   0   1   1   0   0   1   0 . 1   0   1   1   0   0   1   0
-# CMP32DF-SAME:  1   0   1   0   1   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---+-----------+---+-------+---+-------------------------------
-#        BRIEF  DA |    REG    | L | SCALE | 0 |          DISPLACEMENT
-#               ---+-----------+---+-------+---+-------------------------------
-name: MxCMP_RM_ARII
-body: |
-  bb.0:
-    CMP8df  $bd0, 0,  $a0, $d1, implicit-def $ccr
-    CMP8df  $bd0, -1, $a0, $d1, implicit-def $ccr
-    CMP32df  $d0, 0,  $a1, $d1, implicit-def $ccr
-    CMP32df  $d1, 0,  $a2, $a2, implicit-def $ccr
-
-...
---- # ARID
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#       OPWORD   x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-#               ---------------+-----------+-----------+-----------+-----------
-# CMP8DP:        1   0   1   1   0   0   0   0 . 0   0   1   0   1   0   0   0
-# CMP8DP-SAME:   0   0   0   0   0   0   0   0 . 0   0   0   0   0   0   0   0
-#               ---------------------------------------------------------------
-# CMP32DP-SAME:  1   0   1   1   0   0   0   0 . 1   0   1   0   1   0   0   1
-# CMP32DP-SAME:  1   1   1   1   1   1   1   1 . 1   1   1   1   1   1   1   1
-name: MxCMP_RM_ARID
-body: |
-  bb.0:
-    CMP8dp  $bd0, 0,  $a0, implicit-def $ccr
-    CMP32dp  $d0, -1, $a1, implicit-def $ccr
-
-...
---- # ARI
-#               ---------------+-----------+-----------+-----------+-----------
-#                F   E   D   C | B   A   9 | 8   7   6 | 5   4   3 | 2   1   0
-#               ---------------+-----------+-----------+-----------+-----------
-#       OPWORD   x   x   x   x |    REG    |   OPMODE  |    MODE   |    REG
-#               ---------------+-----------+-----------+-----------+-----------
-# CMP8DJ-SAME:   1   0   1   1   0   0   0   0 . 0   0   0   1   0   0   0   0
-#               ---------------------------------------------------------------
-# CMP32DJ-SAME:  1   0   1   1   0   1   1   0 . 1   0   0   1   0   0   0   1
-name: MxCMP_RM_ARI
-body: |
-  bb.0:
-    CMP8dj  $bd0, $a0, implicit-def $ccr
-    CMP32dj  $d3, $a1, implicit-def $ccr
-
-...

diff  --git a/llvm/test/CodeGen/M68k/Encoding/Control/branch-pc-rel.mir b/llvm/test/CodeGen/M68k/Encoding/Control/branch-pc-rel.mir
index fff41ffd087bf..7f7e160ed6cfb 100644
--- a/llvm/test/CodeGen/M68k/Encoding/Control/branch-pc-rel.mir
+++ b/llvm/test/CodeGen/M68k/Encoding/Control/branch-pc-rel.mir
@@ -22,10 +22,10 @@ body: |
       Beq8 %bb.1, implicit $ccr
       BRA8 %bb.2
   bb.1:
-      $d0 = ADD32ri $d0, 0, implicit-def $ccr
+      $d0 = ADD32di $d0, 0, implicit-def $ccr
       RET 0, $d0
   bb.2:
-      $d0 = ADD32ri $d0, 1, implicit-def $ccr
+      $d0 = ADD32di $d0, 1, implicit-def $ccr
       RET 0, $d0
 
 ...

diff  --git a/llvm/test/CodeGen/M68k/Encoding/Relaxations/branch.mir b/llvm/test/CodeGen/M68k/Encoding/Relaxations/branch.mir
index c05d4c51a95c4..73f2fdda4684f 100644
--- a/llvm/test/CodeGen/M68k/Encoding/Relaxations/branch.mir
+++ b/llvm/test/CodeGen/M68k/Encoding/Relaxations/branch.mir
@@ -48,7 +48,7 @@ body: |
       MOV32bb 0, 0, implicit-def $ccr
       MOV32bb 0, 0, implicit-def $ccr
   bb.2:
-      $d0 = ADD32ri $d0, 0, implicit-def $ccr
+      $d0 = ADD32di $d0, 0, implicit-def $ccr
       RET 0, $d0
 
 ...
@@ -90,7 +90,7 @@ body: |
       MOV32bb 0, 0, implicit-def $ccr
       MOV32bb 0, 0, implicit-def $ccr
   bb.2:
-      $d0 = ADD32ri $d0, 0, implicit-def $ccr
+      $d0 = ADD32di $d0, 0, implicit-def $ccr
       RET 0, $d0
 
 ...
@@ -108,7 +108,7 @@ body: |
 
       BRA8 %bb.1
   bb.1:
-      $d0 = ADD32ri $d0, 0, implicit-def $ccr
+      $d0 = ADD32di $d0, 0, implicit-def $ccr
       RET 0, $d0
 
 ...

diff  --git a/llvm/test/CodeGen/M68k/inline-asm.ll b/llvm/test/CodeGen/M68k/inline-asm.ll
index daa412b6e8773..6f9260f23cff6 100644
--- a/llvm/test/CodeGen/M68k/inline-asm.ll
+++ b/llvm/test/CodeGen/M68k/inline-asm.ll
@@ -93,7 +93,7 @@ define void @register_constraints() {
 ; CHECK-LABEL: register_constraints:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0: ; %entry
-; CHECK-NEXT:    sub.l #4, %sp
+; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    ;APP
 ; CHECK-NEXT:    move.l #94, %d0
@@ -107,7 +107,7 @@ define void @register_constraints() {
 ; CHECK-NEXT:    move.l #66, %a0
 ; CHECK-NEXT:    ;NO_APP
 ; CHECK-NEXT:    move.l %a0, (0,%sp)
-; CHECK-NEXT:    add.l #4, %sp
+; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
   %out = alloca i32, align 4

diff  --git a/llvm/test/CodeGen/M68k/varargs.ll b/llvm/test/CodeGen/M68k/varargs.ll
index 4557707e491e8..0fde2bafea5c4 100644
--- a/llvm/test/CodeGen/M68k/varargs.ll
+++ b/llvm/test/CodeGen/M68k/varargs.ll
@@ -9,14 +9,15 @@ define i32 @test(i32 %X, ...) {
 ; CHECK-LABEL: test:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    sub.l #8, %sp
+; CHECK-NEXT:    suba.l #8, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -12
 ; CHECK-NEXT:    lea (16,%sp), %a0
-; CHECK-NEXT:    add.l #4, %a0
-; CHECK-NEXT:    move.l %a0, (4,%sp)
-; CHECK-NEXT:    move.l %a0, (0,%sp)
+; CHECK-NEXT:    move.l %a0, %d0
+; CHECK-NEXT:    add.l #4, %d0
+; CHECK-NEXT:    move.l %d0, (4,%sp)
+; CHECK-NEXT:    move.l %d0, (0,%sp)
 ; CHECK-NEXT:    move.l (16,%sp), %d0
-; CHECK-NEXT:    add.l #8, %sp
+; CHECK-NEXT:    adda.l #8, %sp
 ; CHECK-NEXT:    rts
   %ap = alloca %struct.va_list
   %ap2 = bitcast %struct.va_list* %ap to i8*

diff  --git a/llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRI_xEA.s b/llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRI_xEA.s
new file mode 100644
index 0000000000000..aa832cf8a14fa
--- /dev/null
+++ b/llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRI_xEA.s
@@ -0,0 +1,20 @@
+; RUN: llvm-mc -triple=m68k -show-encoding %s | FileCheck %s
+
+; CHECK:      add.w  #0, %d0
+; CHECK-SAME: encoding: [0xd0,0x7c,0x00,0x00]
+add.w	#0, %d0
+; CHECK:      add.w  #-1, %d3
+; CHECK-SAME: encoding: [0xd6,0x7c,0xff,0xff]
+add.w	#-1, %d3
+; CHECK:      add.l  #-1, %d0
+; CHECK-SAME: encoding: [0xd0,0xbc,0xff,0xff,0xff,0xff]
+add.l	#-1, %d0
+; CHECK:      add.l  #131071, %d0
+; CHECK-SAME: encoding: [0xd0,0xbc,0x00,0x01,0xff,0xff]
+add.l	#131071, %d0
+; CHECK:      add.l  #458752, %d7
+; CHECK-SAME: encoding: [0xde,0xbc,0x00,0x07,0x00,0x00]
+add.l	#458752, %d7
+; CHECK:      adda.l  #0, %a0
+; CHECK-SAME: encoding: [0xd1,0xfc,0x00,0x00,0x00,0x00]
+adda.l   #0, %a0

diff  --git a/llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRM.s b/llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRM.s
new file mode 100644
index 0000000000000..5ca4241e00467
--- /dev/null
+++ b/llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRM.s
@@ -0,0 +1,49 @@
+; RUN: llvm-mc -triple=m68k -show-encoding %s | FileCheck %s
+
+; CHECK:      add.b  (0,%pc,%d1), %d0
+; CHECK-SAME: encoding: [0xd0,0x3b,0x18,0x00]
+add.b	(0,%pc,%d1), %d0
+; CHECK:      add.b  (-1,%pc,%d1), %d0
+; CHECK-SAME: encoding: [0xd0,0x3b,0x18,0xff]
+add.b	(-1,%pc,%d1), %d0
+; CHECK:      add.l  (0,%pc,%d1), %d0
+; CHECK-SAME: encoding: [0xd0,0xbb,0x18,0x00]
+add.l	(0,%pc,%d1), %d0
+; CHECK:      adda.l  (0,%pc,%a2), %a1
+; CHECK-SAME: encoding: [0xd3,0xfb,0xa8,0x00]
+adda.l	(0,%pc,%a2), %a1
+
+; CHECK:      add.b  (0,%pc), %d0
+; CHECK-SAME: encoding: [0xd0,0x3a,0x00,0x00]
+add.b	(0,%pc), %d0
+; CHECK:      add.l  (-1,%pc), %d0
+; CHECK-SAME: encoding: [0xd0,0xba,0xff,0xff]
+add.l	(-1,%pc), %d0
+
+; CHECK:      add.b  (0,%a0,%d1), %d0
+; CHECK-SAME: encoding: [0xd0,0x30,0x18,0x00]
+add.b	(0,%a0,%d1), %d0
+; CHECK:      add.b  (-1,%a0,%d1), %d0
+; CHECK-SAME: encoding: [0xd0,0x30,0x18,0xff]
+add.b	(-1,%a0,%d1), %d0
+; CHECK:      add.l  (0,%a1,%d1), %d0
+; CHECK-SAME: encoding: [0xd0,0xb1,0x18,0x00]
+add.l	(0,%a1,%d1), %d0
+; CHECK:      adda.l  (0,%a2,%a2), %a1
+; CHECK-SAME: encoding: [0xd3,0xf2,0xa8,0x00]
+adda.l	(0,%a2,%a2), %a1
+
+; CHECK:      add.b  (0,%a0), %d0
+; CHECK-SAME: encoding: [0xd0,0x28,0x00,0x00]
+add.b	(0,%a0), %d0
+; CHECK:      add.l  (-1,%a1), %d0
+; CHECK-SAME: encoding: [0xd0,0xa9,0xff,0xff]
+add.l	(-1,%a1), %d0
+
+; CHECK:      add.b  (%a0), %d0
+; CHECK-SAME: encoding: [0xd0,0x10]
+add.b	(%a0), %d0
+; CHECK:      adda.l  (%a1), %a3
+; CHECK-SAME: encoding: [0xd7,0xd1]
+adda.l	(%a1), %a3
+

diff  --git a/llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRR_xEA.s b/llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRR_xEA.s
new file mode 100644
index 0000000000000..fea6a76cbc721
--- /dev/null
+++ b/llvm/test/MC/M68k/Arith/Classes/MxBiArOp_RFRR_xEA.s
@@ -0,0 +1,24 @@
+; RUN: llvm-mc -triple=m68k -show-encoding %s | FileCheck %s
+	.text
+	.globl	MxBiArOp_RFRR_xEA
+; CHECK-LABEL: MxBiArOp_RFRR_xEA:
+MxBiArOp_RFRR_xEA:
+	; CHECK:      add.w  %d1, %d0
+	; CHECK-SAME: encoding: [0xd0,0x41]
+	add.w	%d1, %d0
+	; CHECK:      add.w  %d2, %d3
+	; CHECK-SAME: encoding: [0xd6,0x42]
+	add.w	%d2, %d3
+	; CHECK:      add.l  %d1, %d0
+	; CHECK-SAME: encoding: [0xd0,0x81]
+	add.l	%d1, %d0
+	; CHECK:      add.l  %a1, %d0
+	; CHECK-SAME: encoding: [0xd0,0x89]
+	add.l	%a1, %d0
+	; CHECK:      add.l  %a1, %d7
+	; CHECK-SAME: encoding: [0xde,0x89]
+	add.l	%a1, %d7
+	; CHECK:      adda.l  %d1, %a0
+	; CHECK-SAME: encoding: [0xd1,0xc1]
+	adda.l	%d1, %a0
+

diff  --git a/llvm/test/MC/M68k/Arith/Classes/MxCMP_BI.s b/llvm/test/MC/M68k/Arith/Classes/MxCMP_BI.s
new file mode 100644
index 0000000000000..6686148be411f
--- /dev/null
+++ b/llvm/test/MC/M68k/Arith/Classes/MxCMP_BI.s
@@ -0,0 +1,15 @@
+; RUN: llvm-mc -triple=m68k -motorola-integers -show-encoding %s | FileCheck %s
+
+; CHECK:      cmpi.b  #0, $ffffffffffffffff
+; CHECK-SAME: encoding: [0x0c,0x39,0x00,0x00,0xff,0xff,0xff,0xff]
+cmpi.b	#0, $ffffffffffffffff
+; CHECK:      cmpi.b  #-1, $0
+; CHECK-SAME: encoding: [0x0c,0x39,0x00,0xff,0x00,0x00,0x00,0x00]
+cmpi.b	#-1, $0
+; CHECK:      cmpi.l  #-1, $0
+; CHECK-SAME: encoding: [0x0c,0xb9,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00]
+cmpi.l	#-1, $0
+; CHECK:      cmpi.l  #42, $ffffffffffffffff
+; CHECK-SAME: encoding: [0x0c,0xb9,0x00,0x00,0x00,0x2a,0xff,0xff,0xff,0xff]
+cmpi.l	#42, $ffffffffffffffff
+

diff  --git a/llvm/test/MC/M68k/Arith/Classes/MxCMP_MI.s b/llvm/test/MC/M68k/Arith/Classes/MxCMP_MI.s
new file mode 100644
index 0000000000000..1389956bab6fb
--- /dev/null
+++ b/llvm/test/MC/M68k/Arith/Classes/MxCMP_MI.s
@@ -0,0 +1,67 @@
+; RUN: llvm-mc -triple=m68k -show-encoding %s | FileCheck %s
+
+; CHECK:      cmpi.b  #0, (-1,%pc,%d1)
+; CHECK-SAME: encoding: [0x0c,0x3b,0x00,0x00,0x18,0xff]
+cmpi.b	#0, (-1,%pc,%d1)
+; CHECK:      cmpi.b  #-1, (0,%pc,%d0)
+; CHECK-SAME: encoding: [0x0c,0x3b,0x00,0xff,0x08,0x00]
+cmpi.b	#-1, (0,%pc,%d0)
+; CHECK:      cmpi.l  #-1, (0,%pc,%d7)
+; CHECK-SAME: encoding: [0x0c,0xbb,0xff,0xff,0xff,0xff,0x78,0x00]
+cmpi.l	#-1, (0,%pc,%d7)
+; CHECK:      cmpi.l  #42, (-1,%pc,%d1)
+; CHECK-SAME: encoding: [0x0c,0xbb,0x00,0x00,0x00,0x2a,0x18,0xff]
+cmpi.l	#42, (-1,%pc,%d1)
+
+; CHECK:      cmpi.b  #0, (0,%pc)
+; CHECK-SAME: encoding: [0x0c,0x3a,0x00,0x00,0x00,0x00]
+cmpi.b	#0, (0,%pc)
+; CHECK:      cmpi.b  #-1, (-1,%pc)
+; CHECK-SAME: encoding: [0x0c,0x3a,0x00,0xff,0xff,0xff]
+cmpi.b	#-1, (-1,%pc)
+; CHECK:      cmpi.l  #-1, (0,%pc)
+; CHECK-SAME: encoding: [0x0c,0xba,0xff,0xff,0xff,0xff,0x00,0x00]
+cmpi.l	#-1, (0,%pc)
+; CHECK:      cmpi.l  #42, (0,%pc)
+; CHECK-SAME: encoding: [0x0c,0xba,0x00,0x00,0x00,0x2a,0x00,0x00]
+cmpi.l	#42, (0,%pc)
+
+; CHECK:      cmpi.b  #0, (-1,%a1,%a0)
+; CHECK-SAME: encoding: [0x0c,0x31,0x00,0x00,0x88,0xff]
+cmpi.b	#0, (-1,%a1,%a0)
+; CHECK:      cmpi.b  #-1, (0,%a0,%a0)
+; CHECK-SAME: encoding: [0x0c,0x30,0x00,0xff,0x88,0x00]
+cmpi.b	#-1, (0,%a0,%a0)
+; CHECK:      cmpi.l  #-1, (0,%a6,%a0)
+; CHECK-SAME: encoding: [0x0c,0xb6,0xff,0xff,0xff,0xff,0x88,0x00]
+cmpi.l	#-1, (0,%a6,%a0)
+; CHECK:      cmpi.l  #42, (-1,%a1,%a0)
+; CHECK-SAME: encoding: [0x0c,0xb1,0x00,0x00,0x00,0x2a,0x88,0xff]
+cmpi.l	#42, (-1,%a1,%a0)
+
+; CHECK:      cmpi.b  #0, (-1,%a1)
+; CHECK-SAME: encoding: [0x0c,0x29,0x00,0x00,0xff,0xff]
+cmpi.b	#0, (-1,%a1)
+; CHECK:      cmpi.b  #-1, (0,%a0)
+; CHECK-SAME: encoding: [0x0c,0x28,0x00,0xff,0x00,0x00]
+cmpi.b	#-1, (0,%a0)
+; CHECK:      cmpi.l  #-1, (0,%a6)
+; CHECK-SAME: encoding: [0x0c,0xae,0xff,0xff,0xff,0xff,0x00,0x00]
+cmpi.l	#-1, (0,%a6)
+; CHECK:      cmpi.l  #42, (-1,%a1)
+; CHECK-SAME: encoding: [0x0c,0xa9,0x00,0x00,0x00,0x2a,0xff,0xff]
+cmpi.l	#42, (-1,%a1)
+
+; CHECK:      cmpi.b  #0, (%a1)
+; CHECK-SAME: encoding: [0x0c,0x11,0x00,0x00]
+cmpi.b	#0, (%a1)
+; CHECK:      cmpi.b  #-1, (%a0)
+; CHECK-SAME: encoding: [0x0c,0x10,0x00,0xff]
+cmpi.b	#-1, (%a0)
+; CHECK:      cmpi.l  #-1, (%a6)
+; CHECK-SAME: encoding: [0x0c,0x96,0xff,0xff,0xff,0xff]
+cmpi.l	#-1, (%a6)
+; CHECK:      cmpi.l  #42, (%a1)
+; CHECK-SAME: encoding: [0x0c,0x91,0x00,0x00,0x00,0x2a]
+cmpi.l	#42, (%a1)
+

diff  --git a/llvm/test/MC/M68k/Arith/Classes/MxCMP_RM.s b/llvm/test/MC/M68k/Arith/Classes/MxCMP_RM.s
new file mode 100644
index 0000000000000..0feb1c1793383
--- /dev/null
+++ b/llvm/test/MC/M68k/Arith/Classes/MxCMP_RM.s
@@ -0,0 +1,46 @@
+; RUN: llvm-mc -triple=m68k -show-encoding %s | FileCheck %s
+
+; CHECK:      cmp.b  (0,%pc,%d1), %d0
+; CHECK-SAME: encoding: [0xb0,0x3b,0x18,0x00]
+cmp.b	(0,%pc,%d1), %d0
+; CHECK:      cmp.b  (-1,%pc,%d1), %d0
+; CHECK-SAME: encoding: [0xb0,0x3b,0x18,0xff]
+cmp.b	(-1,%pc,%d1), %d0
+; CHECK:      cmp.l  (0,%pc,%d1), %d0
+; CHECK-SAME: encoding: [0xb0,0xbb,0x18,0x00]
+cmp.l	(0,%pc,%d1), %d0
+
+; CHECK:      cmp.b  (0,%pc), %d0
+; CHECK-SAME: encoding: [0xb0,0x3a,0x00,0x00]
+cmp.b	(0,%pc), %d0
+; CHECK:      cmp.l  (-1,%pc), %d0
+; CHECK-SAME: encoding: [0xb0,0xba,0xff,0xff]
+cmp.l	(-1,%pc), %d0
+
+; CHECK:      cmp.b  (0,%a0,%d1), %d0
+; CHECK-SAME: encoding: [0xb0,0x30,0x18,0x00]
+cmp.b	(0,%a0,%d1), %d0
+; CHECK:      cmp.b  (-1,%a0,%d1), %d0
+; CHECK-SAME: encoding: [0xb0,0x30,0x18,0xff]
+cmp.b	(-1,%a0,%d1), %d0
+; CHECK:      cmp.l  (0,%a1,%d1), %d0
+; CHECK-SAME: encoding: [0xb0,0xb1,0x18,0x00]
+cmp.l	(0,%a1,%d1), %d0
+; CHECK:      cmp.l  (0,%a2,%a2), %d1
+; CHECK-SAME: encoding: [0xb2,0xb2,0xa8,0x00]
+cmp.l	(0,%a2,%a2), %d1
+
+; CHECK:      cmp.b  (0,%a0), %d0
+; CHECK-SAME: encoding: [0xb0,0x28,0x00,0x00]
+cmp.b	(0,%a0), %d0
+; CHECK:      cmp.l  (-1,%a1), %d0
+; CHECK-SAME: encoding: [0xb0,0xa9,0xff,0xff]
+cmp.l	(-1,%a1), %d0
+
+; CHECK:      cmp.b  (%a0), %d0
+; CHECK-SAME: encoding: [0xb0,0x10]
+cmp.b	(%a0), %d0
+; CHECK:      cmp.l  (%a1), %d3
+; CHECK-SAME: encoding: [0xb6,0x91]
+cmp.l	(%a1), %d3
+

diff  --git a/llvm/test/MC/M68k/instructions.s b/llvm/test/MC/M68k/instructions.s
index b6cb210eeaa6e..fd136d1015e94 100644
--- a/llvm/test/MC/M68k/instructions.s
+++ b/llvm/test/MC/M68k/instructions.s
@@ -10,8 +10,8 @@
 
 ; CHECK: move.l %a1, %a0
 move.l %a1, %a0
-; CHECK: add.l %a0, %a1
-add.l %a0, %a1
+; CHECK: adda.l %a0, %a1
+adda.l %a0, %a1
 ; CHECK: addx.l %d1, %d2
 addx.l %d1, %d2
 ; CHECK: sub.w #4, %d1
@@ -32,16 +32,16 @@ seq %d0
 sgt %d0
 ; CHECK: lea (80,%a0), %a1
 lea $50(%a0), %a1
-; CHECK: lsl.l #8, %a1
-lsl.l #8, %a1
-; CHECK: lsr.l #8, %a1
-lsr.l #8, %a1
-; CHECK: asr.l #8, %a1
-asr.l #8, %a1
-; CHECK: rol.l #8, %a1
-rol.l #8, %a1
-; CHECK: ror.l #8, %a1
-ror.l #8, %a1
+; CHECK: lsl.l #8, %d1
+lsl.l #8, %d1
+; CHECK: lsr.l #8, %d1
+lsr.l #8, %d1
+; CHECK: asr.l #8, %d1
+asr.l #8, %d1
+; CHECK: rol.l #8, %d1
+rol.l #8, %d1
+; CHECK: ror.l #8, %d1
+ror.l #8, %d1
 ; CHECK: nop
 nop
 ; CHECK: rts


        


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