[llvm] 5894134 - [RISCV] Autogenerate test. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-08-07T17:11:11-07:00
New Revision: 5894134c6ed843c7a3b03550db5ac2b2bcf6fc98

URL: https://github.com/llvm/llvm-project/commit/5894134c6ed843c7a3b03550db5ac2b2bcf6fc98
DIFF: https://github.com/llvm/llvm-project/commit/5894134c6ed843c7a3b03550db5ac2b2bcf6fc98.diff

LOG: [RISCV] Autogenerate test. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/addimm-mulimm.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
index 6a2b3c3f0e3e..ea08b5ad53ed 100644
--- a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
+++ b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;; Test that (mul (add x, c1), c2) can be transformed to
 ;; (add (mul x, c2), c1*c2) if profitable.
 
@@ -7,14 +8,14 @@
 ; RUN:   | FileCheck -check-prefix=RV64IM %s
 
 define signext i32 @add_mul_trans_accept_1(i32 %x) {
-; RV32IM-LABEL: add_mul_trans_accept_1
+; RV32IM-LABEL: add_mul_trans_accept_1:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi a1, zero, 11
 ; RV32IM-NEXT:    mul a0, a0, a1
 ; RV32IM-NEXT:    addi a0, a0, 407
 ; RV32IM-NEXT:    ret
 ;
-; RV64IM-LABEL: add_mul_trans_accept_1
+; RV64IM-LABEL: add_mul_trans_accept_1:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    addi a1, zero, 11
 ; RV64IM-NEXT:    mul a0, a0, a1
@@ -26,7 +27,7 @@ define signext i32 @add_mul_trans_accept_1(i32 %x) {
 }
 
 define signext i32 @add_mul_trans_accept_2(i32 %x) {
-; RV32IM-LABEL: add_mul_trans_accept_2
+; RV32IM-LABEL: add_mul_trans_accept_2:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi a1, zero, 13
 ; RV32IM-NEXT:    mul a0, a0, a1
@@ -35,7 +36,7 @@ define signext i32 @add_mul_trans_accept_2(i32 %x) {
 ; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
-; RV64IM-LABEL: add_mul_trans_accept_2
+; RV64IM-LABEL: add_mul_trans_accept_2:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    addi a1, zero, 13
 ; RV64IM-NEXT:    mul a0, a0, a1
@@ -49,7 +50,7 @@ define signext i32 @add_mul_trans_accept_2(i32 %x) {
 }
 
 define signext i32 @add_mul_trans_reject_1(i32 %x) {
-; RV32IM-LABEL: add_mul_trans_reject_1
+; RV32IM-LABEL: add_mul_trans_reject_1:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    addi a1, zero, 19
 ; RV32IM-NEXT:    mul a0, a0, a1
@@ -58,7 +59,7 @@ define signext i32 @add_mul_trans_reject_1(i32 %x) {
 ; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
-; RV64IM-LABEL: add_mul_trans_reject_1
+; RV64IM-LABEL: add_mul_trans_reject_1:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    addi a1, zero, 19
 ; RV64IM-NEXT:    mul a0, a0, a1
@@ -72,6 +73,7 @@ define signext i32 @add_mul_trans_reject_1(i32 %x) {
 }
 
 define signext i32 @add_mul_trans_reject_2(i32 %x) {
+; RV32IM-LABEL: add_mul_trans_reject_2:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    lui a1, 792
 ; RV32IM-NEXT:    addi a1, a1, -1709
@@ -81,6 +83,7 @@ define signext i32 @add_mul_trans_reject_2(i32 %x) {
 ; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
+; RV64IM-LABEL: add_mul_trans_reject_2:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    lui a1, 792
 ; RV64IM-NEXT:    addiw a1, a1, -1709