[llvm] d05d4e7 - [NFC][InstCombine] Autogenerate checklines in a few tests being affected by an upcoming change
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 7 07:33:05 PDT 2021
Author: Roman Lebedev
Date: 2021-08-07T17:25:27+03:00
New Revision: d05d4e7f7ebb0c7e61de0857b226710f01aaa13f
URL: https://github.com/llvm/llvm-project/commit/d05d4e7f7ebb0c7e61de0857b226710f01aaa13f
DIFF: https://github.com/llvm/llvm-project/commit/d05d4e7f7ebb0c7e61de0857b226710f01aaa13f.diff
LOG: [NFC][InstCombine] Autogenerate checklines in a few tests being affected by an upcoming change
Added:
Modified:
llvm/test/Transforms/InstCombine/exact.ll
llvm/test/Transforms/InstCombine/sext.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/exact.ll b/llvm/test/Transforms/InstCombine/exact.ll
index 96b6fd689964..6b52dfb0380e 100644
--- a/llvm/test/Transforms/InstCombine/exact.ll
+++ b/llvm/test/Transforms/InstCombine/exact.ll
@@ -3,7 +3,7 @@
define i32 @sdiv1(i32 %x) {
; CHECK-LABEL: @sdiv1(
-; CHECK-NEXT: [[Y:%.*]] = sdiv i32 %x, 8
+; CHECK-NEXT: [[Y:%.*]] = sdiv i32 [[X:%.*]], 8
; CHECK-NEXT: ret i32 [[Y]]
;
%y = sdiv i32 %x, 8
@@ -12,7 +12,7 @@ define i32 @sdiv1(i32 %x) {
define i32 @sdiv2(i32 %x) {
; CHECK-LABEL: @sdiv2(
-; CHECK-NEXT: [[Y:%.*]] = ashr exact i32 %x, 3
+; CHECK-NEXT: [[Y:%.*]] = ashr exact i32 [[X:%.*]], 3
; CHECK-NEXT: ret i32 [[Y]]
;
%y = sdiv exact i32 %x, 8
@@ -21,7 +21,7 @@ define i32 @sdiv2(i32 %x) {
define <2 x i32> @sdiv2_vec(<2 x i32> %x) {
; CHECK-LABEL: @sdiv2_vec(
-; CHECK-NEXT: [[Y:%.*]] = ashr exact <2 x i32> %x, <i32 7, i32 7>
+; CHECK-NEXT: [[Y:%.*]] = ashr exact <2 x i32> [[X:%.*]], <i32 7, i32 7>
; CHECK-NEXT: ret <2 x i32> [[Y]]
;
%y = sdiv exact <2 x i32> %x, <i32 128, i32 128>
@@ -30,8 +30,8 @@ define <2 x i32> @sdiv2_vec(<2 x i32> %x) {
define i32 @sdiv3(i32 %x) {
; CHECK-LABEL: @sdiv3(
-; CHECK-NEXT: [[Y:%.*]] = srem i32 %x, 3
-; CHECK-NEXT: [[Z:%.*]] = sub i32 %x, [[Y]]
+; CHECK-NEXT: [[TMP1:%.*]] = srem i32 [[X:%.*]], 3
+; CHECK-NEXT: [[Z:%.*]] = sub i32 [[X]], [[TMP1]]
; CHECK-NEXT: ret i32 [[Z]]
;
%y = sdiv i32 %x, 3
@@ -41,7 +41,7 @@ define i32 @sdiv3(i32 %x) {
define i32 @sdiv4(i32 %x) {
; CHECK-LABEL: @sdiv4(
-; CHECK-NEXT: ret i32 %x
+; CHECK-NEXT: ret i32 [[X:%.*]]
;
%y = sdiv exact i32 %x, 3
%z = mul i32 %y, 3
@@ -50,8 +50,8 @@ define i32 @sdiv4(i32 %x) {
define i32 @sdiv5(i32 %x) {
; CHECK-LABEL: @sdiv5(
-; CHECK-NEXT: [[Y:%.*]] = srem i32 %x, 3
-; CHECK-NEXT: [[Z:%.*]] = sub i32 [[Y]], %x
+; CHECK-NEXT: [[TMP1:%.*]] = srem i32 [[X:%.*]], 3
+; CHECK-NEXT: [[Z:%.*]] = sub i32 [[TMP1]], [[X]]
; CHECK-NEXT: ret i32 [[Z]]
;
%y = sdiv i32 %x, 3
@@ -61,7 +61,7 @@ define i32 @sdiv5(i32 %x) {
define i32 @sdiv6(i32 %x) {
; CHECK-LABEL: @sdiv6(
-; CHECK-NEXT: [[Z:%.*]] = sub i32 0, %x
+; CHECK-NEXT: [[Z:%.*]] = sub i32 0, [[X:%.*]]
; CHECK-NEXT: ret i32 [[Z]]
;
%y = sdiv exact i32 %x, 3
@@ -71,7 +71,7 @@ define i32 @sdiv6(i32 %x) {
define i32 @udiv1(i32 %x, i32 %w) {
; CHECK-LABEL: @udiv1(
-; CHECK-NEXT: ret i32 %x
+; CHECK-NEXT: ret i32 [[X:%.*]]
;
%y = udiv exact i32 %x, %w
%z = mul i32 %y, %w
@@ -80,7 +80,7 @@ define i32 @udiv1(i32 %x, i32 %w) {
define i32 @udiv2(i32 %x, i32 %w) {
; CHECK-LABEL: @udiv2(
-; CHECK-NEXT: [[Z:%.*]] = lshr exact i32 %x, %w
+; CHECK-NEXT: [[Z:%.*]] = lshr exact i32 [[X:%.*]], [[W:%.*]]
; CHECK-NEXT: ret i32 [[Z]]
;
%y = shl i32 1, %w
@@ -90,7 +90,7 @@ define i32 @udiv2(i32 %x, i32 %w) {
define i64 @ashr1(i64 %X) {
; CHECK-LABEL: @ashr1(
-; CHECK-NEXT: [[A:%.*]] = shl i64 %X, 8
+; CHECK-NEXT: [[A:%.*]] = shl i64 [[X:%.*]], 8
; CHECK-NEXT: [[B:%.*]] = ashr exact i64 [[A]], 2
; CHECK-NEXT: ret i64 [[B]]
;
@@ -103,7 +103,7 @@ define i64 @ashr1(i64 %X) {
define <2 x i64> @ashr1_vec(<2 x i64> %X) {
; CHECK-LABEL: @ashr1_vec(
-; CHECK-NEXT: [[A:%.*]] = shl <2 x i64> %X, <i64 8, i64 8>
+; CHECK-NEXT: [[A:%.*]] = shl <2 x i64> [[X:%.*]], <i64 8, i64 8>
; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i64> [[A]], <i64 2, i64 2>
; CHECK-NEXT: ret <2 x i64> [[B]]
;
@@ -115,7 +115,7 @@ define <2 x i64> @ashr1_vec(<2 x i64> %X) {
; PR9120
define i1 @ashr_icmp1(i64 %X) {
; CHECK-LABEL: @ashr_icmp1(
-; CHECK-NEXT: [[B:%.*]] = icmp eq i64 %X, 0
+; CHECK-NEXT: [[B:%.*]] = icmp eq i64 [[X:%.*]], 0
; CHECK-NEXT: ret i1 [[B]]
;
%A = ashr exact i64 %X, 2 ; X/4
@@ -125,7 +125,7 @@ define i1 @ashr_icmp1(i64 %X) {
define i1 @ashr_icmp2(i64 %X) {
; CHECK-LABEL: @ashr_icmp2(
-; CHECK-NEXT: [[Z:%.*]] = icmp slt i64 %X, 16
+; CHECK-NEXT: [[Z:%.*]] = icmp slt i64 [[X:%.*]], 16
; CHECK-NEXT: ret i1 [[Z]]
;
%Y = ashr exact i64 %X, 2 ; x / 4
@@ -135,7 +135,7 @@ define i1 @ashr_icmp2(i64 %X) {
define <2 x i1> @ashr_icmp2_vec(<2 x i64> %X) {
; CHECK-LABEL: @ashr_icmp2_vec(
-; CHECK-NEXT: [[Z:%.*]] = icmp slt <2 x i64> %X, <i64 16, i64 16>
+; CHECK-NEXT: [[Z:%.*]] = icmp slt <2 x i64> [[X:%.*]], <i64 16, i64 16>
; CHECK-NEXT: ret <2 x i1> [[Z]]
;
%Y = ashr exact <2 x i64> %X, <i64 2, i64 2>
@@ -147,7 +147,7 @@ define <2 x i1> @ashr_icmp2_vec(<2 x i64> %X) {
; Make sure we don't transform the ashr here into an sdiv
define i1 @pr9998(i32 %V) {
; CHECK-LABEL: @pr9998(
-; CHECK-NEXT: [[W_MASK:%.*]] = and i32 %V, 1
+; CHECK-NEXT: [[W_MASK:%.*]] = and i32 [[V:%.*]], 1
; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[W_MASK]], 0
; CHECK-NEXT: ret i1 [[Z]]
;
@@ -161,7 +161,7 @@ define i1 @pr9998(i32 %V) {
; FIXME: Vectors should fold the same way.
define <2 x i1> @pr9998vec(<2 x i32> %V) {
; CHECK-LABEL: @pr9998vec(
-; CHECK-NEXT: [[W:%.*]] = shl <2 x i32> %V, <i32 31, i32 31>
+; CHECK-NEXT: [[W:%.*]] = shl <2 x i32> [[V:%.*]], <i32 31, i32 31>
; CHECK-NEXT: [[X:%.*]] = ashr exact <2 x i32> [[W]], <i32 31, i32 31>
; CHECK-NEXT: [[Y:%.*]] = sext <2 x i32> [[X]] to <2 x i64>
; CHECK-NEXT: [[Z:%.*]] = icmp ugt <2 x i64> [[Y]], <i64 7297771788697658747, i64 7297771788697658747>
@@ -176,7 +176,7 @@ define <2 x i1> @pr9998vec(<2 x i32> %V) {
define i1 @udiv_icmp1(i64 %X) {
; CHECK-LABEL: @udiv_icmp1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 %X, 0
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[X:%.*]], 0
; CHECK-NEXT: ret i1 [[TMP1]]
;
%A = udiv exact i64 %X, 5 ; X/5
@@ -186,7 +186,7 @@ define i1 @udiv_icmp1(i64 %X) {
define <2 x i1> @udiv_icmp1_vec(<2 x i64> %X) {
; CHECK-LABEL: @udiv_icmp1_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i64> %X, zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i64> [[X:%.*]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%A = udiv exact <2 x i64> %X, <i64 5, i64 5>
@@ -196,7 +196,7 @@ define <2 x i1> @udiv_icmp1_vec(<2 x i64> %X) {
define i1 @udiv_icmp2(i64 %X) {
; CHECK-LABEL: @udiv_icmp2(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 0
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], 0
; CHECK-NEXT: ret i1 [[TMP1]]
;
%A = udiv exact i64 %X, 5 ; X/5 == 0 --> x == 0
@@ -206,7 +206,7 @@ define i1 @udiv_icmp2(i64 %X) {
define <2 x i1> @udiv_icmp2_vec(<2 x i64> %X) {
; CHECK-LABEL: @udiv_icmp2_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%A = udiv exact <2 x i64> %X, <i64 5, i64 5>
@@ -216,7 +216,7 @@ define <2 x i1> @udiv_icmp2_vec(<2 x i64> %X) {
define i1 @sdiv_icmp1(i64 %X) {
; CHECK-LABEL: @sdiv_icmp1(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 0
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], 0
; CHECK-NEXT: ret i1 [[TMP1]]
;
%A = sdiv exact i64 %X, 5 ; X/5 == 0 --> x == 0
@@ -226,7 +226,7 @@ define i1 @sdiv_icmp1(i64 %X) {
define <2 x i1> @sdiv_icmp1_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp1_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
@@ -236,7 +236,7 @@ define <2 x i1> @sdiv_icmp1_vec(<2 x i64> %X) {
define i1 @sdiv_icmp2(i64 %X) {
; CHECK-LABEL: @sdiv_icmp2(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 5
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], 5
; CHECK-NEXT: ret i1 [[TMP1]]
;
%A = sdiv exact i64 %X, 5 ; X/5 == 1 --> x == 5
@@ -246,7 +246,7 @@ define i1 @sdiv_icmp2(i64 %X) {
define <2 x i1> @sdiv_icmp2_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp2_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 5, i64 5>
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 5, i64 5>
; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
@@ -256,7 +256,7 @@ define <2 x i1> @sdiv_icmp2_vec(<2 x i64> %X) {
define i1 @sdiv_icmp3(i64 %X) {
; CHECK-LABEL: @sdiv_icmp3(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, -5
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], -5
; CHECK-NEXT: ret i1 [[TMP1]]
;
%A = sdiv exact i64 %X, 5 ; X/5 == -1 --> x == -5
@@ -266,7 +266,7 @@ define i1 @sdiv_icmp3(i64 %X) {
define <2 x i1> @sdiv_icmp3_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp3_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 -5, i64 -5>
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 -5, i64 -5>
; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
@@ -276,7 +276,7 @@ define <2 x i1> @sdiv_icmp3_vec(<2 x i64> %X) {
define i1 @sdiv_icmp4(i64 %X) {
; CHECK-LABEL: @sdiv_icmp4(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 0
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], 0
; CHECK-NEXT: ret i1 [[TMP1]]
;
%A = sdiv exact i64 %X, -5 ; X/-5 == 0 --> x == 0
@@ -286,7 +286,7 @@ define i1 @sdiv_icmp4(i64 %X) {
define <2 x i1> @sdiv_icmp4_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp4_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
@@ -296,7 +296,7 @@ define <2 x i1> @sdiv_icmp4_vec(<2 x i64> %X) {
define i1 @sdiv_icmp5(i64 %X) {
; CHECK-LABEL: @sdiv_icmp5(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, -5
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], -5
; CHECK-NEXT: ret i1 [[TMP1]]
;
%A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == -5
@@ -306,7 +306,7 @@ define i1 @sdiv_icmp5(i64 %X) {
define <2 x i1> @sdiv_icmp5_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp5_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 -5, i64 -5>
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 -5, i64 -5>
; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
@@ -316,7 +316,7 @@ define <2 x i1> @sdiv_icmp5_vec(<2 x i64> %X) {
define i1 @sdiv_icmp6(i64 %X) {
; CHECK-LABEL: @sdiv_icmp6(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 5
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X:%.*]], 5
; CHECK-NEXT: ret i1 [[TMP1]]
;
%A = sdiv exact i64 %X, -5 ; X/-5 == -1 --> x == 5
@@ -326,7 +326,7 @@ define i1 @sdiv_icmp6(i64 %X) {
define <2 x i1> @sdiv_icmp6_vec(<2 x i64> %X) {
; CHECK-LABEL: @sdiv_icmp6_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 5, i64 5>
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[X:%.*]], <i64 5, i64 5>
; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
diff --git a/llvm/test/Transforms/InstCombine/sext.ll b/llvm/test/Transforms/InstCombine/sext.ll
index ebab23a19525..04573e2e8ddc 100644
--- a/llvm/test/Transforms/InstCombine/sext.ll
+++ b/llvm/test/Transforms/InstCombine/sext.ll
@@ -9,7 +9,7 @@ declare i32 @llvm.cttz.i32(i32, i1)
define i64 @test1(i32 %x) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), [[RNG0:!range !.*]]
+; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
; CHECK-NEXT: ret i64 [[S]]
;
@@ -20,7 +20,7 @@ define i64 @test1(i32 %x) {
define i64 @test2(i32 %x) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]]
; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
; CHECK-NEXT: ret i64 [[S]]
;
@@ -31,7 +31,7 @@ define i64 @test2(i32 %x) {
define i64 @test3(i32 %x) {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), [[RNG0]]
+; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]]
; CHECK-NEXT: [[S:%.*]] = zext i32 [[T]] to i64
; CHECK-NEXT: ret i64 [[S]]
;
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