[PATCH] D107692: [DAGCombine] Prevent the transform of combine for multi-use operand

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:4944
   if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
-      VT.getSizeInBits() <= 64) {
+      VT.getSizeInBits() <= 64 && N0.hasOneUse()) {
     if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
----------------
N0->hasOneUse() would probably be better, to check the Node has one use not the SDValue. (Although here it likely won't make much difference.)


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Comment at: llvm/test/CodeGen/AArch64/arm64-srl-and.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=tsv110 -O3 < %s | FileCheck %s
+
----------------
This needs a triple, and likely doesn't need a -mcpu.


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Comment at: llvm/test/CodeGen/AArch64/arm64-srl-and.ll:11
+; CHECK-NEXT:    add w8, w8, w9
+; CHECK-NEXT:    and w0, w8, w8, lsr #16
+entry:
----------------
Has this deleted some of the check lines?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107692/new/

https://reviews.llvm.org/D107692