[llvm] 62fe3dc - Fix PPC buildbot break caused by 4c4093e6e39fe6601f9c95a95a6bc242ef648cd5
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 6 20:10:30 PDT 2021
Author: Nemanja Ivanovic
Date: 2021-08-06T22:10:20-05:00
New Revision: 62fe3dcf98d17ea027492fd723dbb9b6dc295761
URL: https://github.com/llvm/llvm-project/commit/62fe3dcf98d17ea027492fd723dbb9b6dc295761
DIFF: https://github.com/llvm/llvm-project/commit/62fe3dcf98d17ea027492fd723dbb9b6dc295761.diff
LOG: Fix PPC buildbot break caused by 4c4093e6e39fe6601f9c95a95a6bc242ef648cd5
This commit adds the isnan intrinsic and provides a default expansion
for it in the SDAG. However, it makes the assumption that types
it operates on are IEEE-compliant types. This is not always the case.
An example of that is PPC "double double" which has a representation
that
- Does not need to conform to IEEE requirements for isnan as it is
not an IEEE-compliant type
- Does not have a representation that allows for straightforward
reinterpreting as an integer and use of integer operations
The result was that this commit broke __builtin_isnan for ppc_fp128
making many valid numeric values report a NaN.
This patch simply changes the expansion to always expand to unordered
comparison (regardless of whether FP exceptions are tracked). This
is inline with previous semantics.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/PowerPC/ppc-fpclass.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 52e81f29d014a..dd282a3beae83 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -6976,8 +6976,9 @@ SDValue TargetLowering::expandISNAN(EVT ResultVT, SDValue Op, SDNodeFlags Flags,
assert(OperandVT.isFloatingPoint());
// If floating point exceptions are ignored, expand to unordered comparison.
- if (Flags.hasNoFPExcept() &&
- isOperationLegalOrCustom(ISD::SETCC, OperandVT.getScalarType()))
+ if ((Flags.hasNoFPExcept() &&
+ isOperationLegalOrCustom(ISD::SETCC, OperandVT.getScalarType())) ||
+ OperandVT == MVT::ppcf128)
return DAG.getSetCC(DL, ResultVT, Op, DAG.getConstantFP(0.0, DL, OperandVT),
ISD::SETUO);
diff --git a/llvm/test/CodeGen/PowerPC/ppc-fpclass.ll b/llvm/test/CodeGen/PowerPC/ppc-fpclass.ll
index 40794aa3ca5f2..5924defaa9396 100644
--- a/llvm/test/CodeGen/PowerPC/ppc-fpclass.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-fpclass.ll
@@ -37,39 +37,15 @@ entry:
define i1 @isnan_ldouble(ppc_fp128 %x) nounwind {
; CHECK-LABEL: isnan_ldouble:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: stwu 1, -32(1)
-; CHECK-NEXT: stfd 1, 16(1)
-; CHECK-NEXT: lis 3, 32752
-; CHECK-NEXT: lwz 4, 20(1)
-; CHECK-NEXT: stfd 2, 24(1)
-; CHECK-NEXT: lwz 5, 28(1)
-; CHECK-NEXT: cmplw 1, 4, 3
-; CHECK-NEXT: lwz 3, 24(1)
-; CHECK-NEXT: xoris 4, 4, 32752
-; CHECK-NEXT: lwz 6, 16(1)
-; CHECK-NEXT: clrlwi. 5, 5, 1
-; CHECK-NEXT: cmplwi 5, 5, 0
-; CHECK-NEXT: crandc 24, 1, 22
-; CHECK-NEXT: cmpwi 3, 0
-; CHECK-NEXT: crandc 20, 22, 2
-; CHECK-NEXT: cmpwi 6, 0
-; CHECK-NEXT: cmplwi 7, 4, 0
-; CHECK-NEXT: or 3, 3, 5
-; CHECK-NEXT: crandc 21, 5, 30
-; CHECK-NEXT: crandc 22, 30, 2
-; CHECK-NEXT: cmplwi 3, 0
-; CHECK-NEXT: cror 20, 20, 24
-; CHECK-NEXT: cror 21, 22, 21
-; CHECK-NEXT: crandc 20, 20, 2
-; CHECK-NEXT: crand 21, 2, 21
-; CHECK-NEXT: crnor 20, 21, 20
+; CHECK-NEXT: fcmpu 0, 1, 1
+; CHECK-NEXT: fcmpu 1, 2, 2
+; CHECK-NEXT: crandc 20, 7, 3
; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: crnor 20, 3, 20
; CHECK-NEXT: bc 12, 20, .LBB2_1
-; CHECK-NEXT: b .LBB2_2
+; CHECK-NEXT: blr
; CHECK-NEXT: .LBB2_1: # %entry
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: .LBB2_2: # %entry
-; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: blr
entry:
%0 = tail call i1 @llvm.isnan.ppcf128(ppc_fp128 %x)
@@ -132,39 +108,15 @@ entry:
define i1 @isnan_ldouble_strictfp(ppc_fp128 %x) strictfp nounwind {
; CHECK-LABEL: isnan_ldouble_strictfp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: stwu 1, -32(1)
-; CHECK-NEXT: stfd 1, 16(1)
-; CHECK-NEXT: lis 3, 32752
-; CHECK-NEXT: lwz 4, 20(1)
-; CHECK-NEXT: stfd 2, 24(1)
-; CHECK-NEXT: lwz 5, 28(1)
-; CHECK-NEXT: cmplw 1, 4, 3
-; CHECK-NEXT: lwz 3, 24(1)
-; CHECK-NEXT: xoris 4, 4, 32752
-; CHECK-NEXT: lwz 6, 16(1)
-; CHECK-NEXT: clrlwi. 5, 5, 1
-; CHECK-NEXT: cmplwi 5, 5, 0
-; CHECK-NEXT: crandc 24, 1, 22
-; CHECK-NEXT: cmpwi 3, 0
-; CHECK-NEXT: crandc 20, 22, 2
-; CHECK-NEXT: cmpwi 6, 0
-; CHECK-NEXT: cmplwi 7, 4, 0
-; CHECK-NEXT: or 3, 3, 5
-; CHECK-NEXT: crandc 21, 5, 30
-; CHECK-NEXT: crandc 22, 30, 2
-; CHECK-NEXT: cmplwi 3, 0
-; CHECK-NEXT: cror 20, 20, 24
-; CHECK-NEXT: cror 21, 22, 21
-; CHECK-NEXT: crandc 20, 20, 2
-; CHECK-NEXT: crand 21, 2, 21
-; CHECK-NEXT: crnor 20, 21, 20
+; CHECK-NEXT: fcmpu 0, 1, 1
+; CHECK-NEXT: fcmpu 1, 2, 2
+; CHECK-NEXT: crandc 20, 7, 3
; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: crnor 20, 3, 20
; CHECK-NEXT: bc 12, 20, .LBB5_1
-; CHECK-NEXT: b .LBB5_2
+; CHECK-NEXT: blr
; CHECK-NEXT: .LBB5_1: # %entry
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: .LBB5_2: # %entry
-; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: blr
entry:
%0 = tail call i1 @llvm.isnan.ppcf128(ppc_fp128 %x)
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