[PATCH] D106449: [amdgpu] Handle the case where there is no scavenged register.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:586
   /// Insert an unconditional indirect branch at the end of \p MBB to \p
-  /// NewDestBB.  \p BrOffset indicates the offset of \p NewDestBB relative to
+  /// NewDestBB. Optiionally, insert the clobbered register restoring in \p
+  /// RestoreBB. \p BrOffset indicates the offset of \p NewDestBB relative to
----------------
typo Optiionally


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Comment at: llvm/lib/CodeGen/BranchRelaxation.cpp:484-485
+    // restore blocks are just duplicated for each far branch.
+    if (DestBB->isEntryBlock()) {
+      // If DestBB is the entry block, create a new empty entry block falling
+      // through into DestBB.
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I'm pretty sure this is illegal, you can't have a branch to the entry block


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Comment at: llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll:331
+; CHECK-NEXT:    s_not_b64 exec, exec
+; CHECK-NEXT:    buffer_store_dword v0, off, s[96:99], 0
+; CHECK-NEXT:    v_writelane_b32 v0, s0, 0
----------------
Where did this frame index come from?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106449/new/

https://reviews.llvm.org/D106449