[PATCH] D107642: [ARM] Enable subreg liveness

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samtebbs, NickGuy, simon_tatham, ostannard.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
dmgreen requested review of this revision.
Herald added a project: LLVM.

This enables subreg liveness in the arm backend when MVE is present, which allows the register allocator to detect when subregister are alive/dead, compared to only acting on full registers. This can helps produce better code on MVE with the way MQPR registers are made up of SPR registers, but is especially helpful for MQQPR and MQQQQPR registers, where there are very few "registers" available and being able to split them up into subregs can help produce much better code.

For MQQPR and MQQQQPR we currently spill them using VLDMDIA with d-subregs for each part. This doesn't pass verifier checks as the constituent parts can sometimes be undefined at point of use. So this patch also adds MQQPRLoad and MQQPRStore pseudo instructions that can take the entire register and be lowered later in the pipeline. They still end up as VLDMIA/VSTMIA instructions, but hold the original larger register. This has the added benefit that we can more easily return the correct value from isStoreToStackSlot, allowing the regallocator to potentially produce better code.


https://reviews.llvm.org/D107642

Files:
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll
  llvm/test/CodeGen/Thumb2/active_lane_mask.ll
  llvm/test/CodeGen/Thumb2/mve-be.ll
  llvm/test/CodeGen/Thumb2/mve-ctlz.ll
  llvm/test/CodeGen/Thumb2/mve-ctpop.ll
  llvm/test/CodeGen/Thumb2/mve-cttz.ll
  llvm/test/CodeGen/Thumb2/mve-div-expand.ll
  llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-fmas.ll
  llvm/test/CodeGen/Thumb2/mve-fmath.ll
  llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll
  llvm/test/CodeGen/Thumb2/mve-frint.ll
  llvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll
  llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/vld24.ll
  llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
  llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
  llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
  llvm/test/CodeGen/Thumb2/mve-masked-store.ll
  llvm/test/CodeGen/Thumb2/mve-minmax.ll
  llvm/test/CodeGen/Thumb2/mve-nofloat.ll
  llvm/test/CodeGen/Thumb2/mve-phireg.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
  llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
  llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll
  llvm/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll
  llvm/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll
  llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll
  llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
  llvm/test/CodeGen/Thumb2/mve-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
  llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
  llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
  llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll
  llvm/test/CodeGen/Thumb2/mve-vabdus.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
  llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
  llvm/test/CodeGen/Thumb2/mve-vcvt.ll
  llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
  llvm/test/CodeGen/Thumb2/mve-vdup.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
  llvm/test/CodeGen/Thumb2/mve-vhadd.ll
  llvm/test/CodeGen/Thumb2/mve-vld2-post.ll
  llvm/test/CodeGen/Thumb2/mve-vld2.ll
  llvm/test/CodeGen/Thumb2/mve-vld3.ll
  llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
  llvm/test/CodeGen/Thumb2/mve-vld4.ll
  llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll
  llvm/test/CodeGen/Thumb2/mve-vmovn.ll
  llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll
  llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll
  llvm/test/CodeGen/Thumb2/mve-vst2-post.ll
  llvm/test/CodeGen/Thumb2/mve-vst2.ll
  llvm/test/CodeGen/Thumb2/mve-vst3.ll
  llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
  llvm/test/CodeGen/Thumb2/mve-vst4.ll
  llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll