[PATCH] D107639: [AMDGPU][GISel] Smaller code for scalar 32 to 64-bit extensions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

I thought these got up split before selection



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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:2100
+      Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
+      unsigned SubReg = InReg ? AMDGPU::sub0 : 0;
+      if (Signed)
----------------
s/0/AMDGPU::NoSubRegister


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:2101
+      unsigned SubReg = InReg ? AMDGPU::sub0 : 0;
+      if (Signed)
+        BuildMI(MBB, I, DL, TII.get(AMDGPU::S_ASHR_I32), HiReg)
----------------
Braces


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:2105
+          .addImm(31);
+      else
+        BuildMI(MBB, I, DL, TII.get(AMDGPU::S_MOV_B32), HiReg)
----------------
Braces


Repository:
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  https://reviews.llvm.org/D107639/new/

https://reviews.llvm.org/D107639