[PATCH] D107009: [WIP][X86] combineX86ShuffleChain(): canonicalize mask elts picking from splats

Thu Aug 5 11:34:01 PDT 2021

lebedev.ri reopened this revision.
lebedev.ri marked an inline comment as done.
lebedev.ri added a comment.
This revision is now accepted and ready to land.

This was reverted in rGbd17ced1db9a674fc8aa6632899e245672c7aa35 <https://reviews.llvm.org/rGbd17ced1db9a674fc8aa6632899e245672c7aa35>.

  <and so on>

  Legalizing: t300: v4i32,ch = X86ISD::VBROADCAST_LOAD<(load (s32) from %ir.input + 48, align 16)> t0, t302
  Legal node: nothing to do

  Combining: t300: v4i32,ch = X86ISD::VBROADCAST_LOAD<(load (s32) from %ir.input + 48, align 16)> t0, t302

  Legalizing: t2574: v4i32 = X86ISD::UNPCKL t250, t300
  Legal node: nothing to do

  Combining: t2574: v4i32 = X86ISD::UNPCKL t250, t300
  Creating constant: t2575: i8 = TargetConstant<10>
  Creating new node: t2576: v4i32 = X86ISD::BLENDI t250, t300, TargetConstant:i8<10>
   ... into: t2576: v4i32 = X86ISD::BLENDI t250, t300, TargetConstant:i8<10>

  Legalizing: t250: v4i32 = extract_subvector t259, Constant:i64<0>
  Legal node: nothing to do

  Combining: t250: v4i32 = extract_subvector t259, Constant:i64<0>

  Legalizing: t300: v4i32,ch = X86ISD::VBROADCAST_LOAD<(load (s32) from %ir.input + 48, align 16)> t0, t302
  Legal node: nothing to do

  Combining: t300: v4i32,ch = X86ISD::VBROADCAST_LOAD<(load (s32) from %ir.input + 48, align 16)> t0, t302

  Legalizing: t2576: v4i32 = X86ISD::BLENDI t250, t300, TargetConstant:i8<10>
  Legal node: nothing to do

  Combining: t2576: v4i32 = X86ISD::BLENDI t250, t300, TargetConstant:i8<10>

  Legalizing: t2575: i8 = TargetConstant<10>

  Combining: t2575: i8 = TargetConstant<10>

  Legalizing: t253: v8i32 = insert_subvector undef:v8i32, t2576, Constant:i64<0>
  Legal node: nothing to do

  Combining: t253: v8i32 = insert_subvector undef:v8i32, t2576, Constant:i64<0>

  Legalizing: t295: v4i32 = X86ISD::BLENDI t194, t195, TargetConstant:i8<12>
  Legal node: nothing to do

  Combining: t295: v4i32 = X86ISD::BLENDI t194, t195, TargetConstant:i8<12>
  Creating new node: t2577: v4i32 = X86ISD::UNPCKL t250, t300

  Replacing.2 t2576: v4i32 = X86ISD::BLENDI t250, t300, TargetConstant:i8<10>

  With: t2577: v4i32 = X86ISD::UNPCKL t250, t300

  <and so on>

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107009/new/

https://reviews.llvm.org/D107009