[llvm] f3f3098 - [AArch64][GlobalISel] Mark v16s8 <- v8s8, v8s8 G_CONCAT_VECTOR as legal

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2021-08-05T09:40:46-07:00
New Revision: f3f3098afe1ca21671922e39328f127e79b7dd3c

URL: https://github.com/llvm/llvm-project/commit/f3f3098afe1ca21671922e39328f127e79b7dd3c
DIFF: https://github.com/llvm/llvm-project/commit/f3f3098afe1ca21671922e39328f127e79b7dd3c.diff

LOG: [AArch64][GlobalISel] Mark v16s8 <- v8s8, v8s8 G_CONCAT_VECTOR as legal

G_CONCAT_VECTORS shows up from time to time when legalizing other instructions.

We actually import patterns for the v16s8 <- v8s8, v8s8 case so marking it
as legal gives us selection for free.

Differential Revision: https://reviews.llvm.org/D107512

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
    llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 2384b1ee8cf04..f6515f6ae4427 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -723,7 +723,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .clampNumElements(0, v2s64, v2s64);
 
   getActionDefinitionsBuilder(G_CONCAT_VECTORS)
-      .legalFor({{v4s32, v2s32}, {v8s16, v4s16}});
+      .legalFor({{v4s32, v2s32}, {v8s16, v4s16}, {v16s8, v8s8}});
 
   getActionDefinitionsBuilder(G_JUMP_TABLE).legalFor({{p0}, {s64}});
 

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
index 723be5a716b35..3263fdcdee662 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-concat-vectors.mir
@@ -1,12 +1,14 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -global-isel-abort=1 -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -global-isel-abort=1 -verify-machineinstrs -o - | FileCheck %s
 
 ---
 name:            legal_v4s32_v2s32
+tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $d0, $d1
     ; CHECK-LABEL: name: legal_v4s32_v2s32
+    ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
     ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[COPY]](<2 x s32>), [[COPY1]](<2 x s32>)
@@ -20,10 +22,12 @@ body: |
 ...
 ---
 name:            legal_v8s16_v4s16
+tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $d0, $d1
     ; CHECK-LABEL: name: legal_v8s16_v4s16
+    ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
     ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[COPY]](<4 x s16>), [[COPY1]](<4 x s16>)
@@ -35,3 +39,22 @@ body: |
     $q0 = COPY %2(<8 x s16>)
     RET_ReallyLR
 ...
+---
+name:            legal_v16s8_v8s8
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: legal_v16s8_v8s8
+    ; CHECK: liveins: $q0
+    ; CHECK: %a:_(<8 x s8>) = G_IMPLICIT_DEF
+    ; CHECK: %b:_(<8 x s8>) = G_IMPLICIT_DEF
+    ; CHECK: %concat:_(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)
+    ; CHECK: $q0 = COPY %concat(<16 x s8>)
+    ; CHECK: RET_ReallyLR implicit $q0
+    %a:_(<8 x s8>) = G_IMPLICIT_DEF
+    %b:_(<8 x s8>) = G_IMPLICIT_DEF
+    %concat:_(<16 x s8>) = G_CONCAT_VECTORS %a:_(<8 x s8>), %b:_(<8 x s8>)
+    $q0 = COPY %concat(<16 x s8>)
+    RET_ReallyLR implicit $q0
+...

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
index 2fdec4a62f657..439bd2066b930 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir
@@ -67,3 +67,52 @@ body:             |
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            select_v16s8_v8s8_undef
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0
+
+    ; CHECK-LABEL: name: select_v16s8_v8s8_undef
+    ; CHECK: liveins: $q0
+    ; CHECK: %a:fpr64 = IMPLICIT_DEF
+    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+    ; CHECK: %concat:fpr128 = INSERT_SUBREG [[DEF]], %a, %subreg.dsub
+    ; CHECK: $q0 = COPY %concat
+    ; CHECK: RET_ReallyLR implicit $q0
+    %a:fpr(<8 x s8>) = G_IMPLICIT_DEF
+    %b:fpr(<8 x s8>) = G_IMPLICIT_DEF
+    %concat:fpr(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)
+    $q0 = COPY %concat(<16 x s8>)
+    RET_ReallyLR implicit $q0
+
+...
+---
+name:            select_v16s8_v8s8_not_undef
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0, $d1
+    ; CHECK-LABEL: name: select_v16s8_v8s8_not_undef
+    ; CHECK: liveins: $q0, $d1
+    ; CHECK: %a:fpr64 = COPY $d0
+    ; CHECK: %b:fpr64 = COPY $d1
+    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %b, %subreg.dsub
+    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], %a, %subreg.dsub
+    ; CHECK: %concat:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
+    ; CHECK: $q0 = COPY %concat
+    ; CHECK: RET_ReallyLR implicit $q0
+    %a:fpr(<8 x s8>) = COPY $d0
+    %b:fpr(<8 x s8>) = COPY $d1
+    %concat:fpr(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)
+    $q0 = COPY %concat(<16 x s8>)
+    RET_ReallyLR implicit $q0
+
+...