[llvm] fe6ae81 - [InstCombine] Fix vscale zext/sext optimization when vscale_range is unbounded.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 4 09:17:59 PDT 2021
Author: Sander de Smalen
Date: 2021-08-04T17:17:37+01:00
New Revision: fe6ae81ef3644bf216c9ca8d2c90150cd9f83a57
URL: https://github.com/llvm/llvm-project/commit/fe6ae81ef3644bf216c9ca8d2c90150cd9f83a57
DIFF: https://github.com/llvm/llvm-project/commit/fe6ae81ef3644bf216c9ca8d2c90150cd9f83a57.diff
LOG: [InstCombine] Fix vscale zext/sext optimization when vscale_range is unbounded.
According to the LangRef, a (vscale_range) value of 0 means unbounded.
This patch additionally cleans up the test file vscale_sext_and_zext.ll.
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
llvm/test/Transforms/InstCombine/vscale_sext_and_zext.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
index cad25ff3cd367..ce533f33f65a4 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -1368,7 +1368,7 @@ Instruction *InstCombinerImpl::visitZExt(ZExtInst &CI) {
.getVScaleRangeArgs()
.second;
unsigned TypeWidth = Src->getType()->getScalarSizeInBits();
- if (Log2_32(MaxVScale) < TypeWidth) {
+ if (MaxVScale > 0 && Log2_32(MaxVScale) < TypeWidth) {
Value *VScale = Builder.CreateVScale(ConstantInt::get(DestTy, 1));
return replaceInstUsesWith(CI, VScale);
}
@@ -1625,8 +1625,7 @@ Instruction *InstCombinerImpl::visitSExt(SExtInst &CI) {
->getFnAttribute(Attribute::VScaleRange)
.getVScaleRangeArgs()
.second;
- unsigned TypeWidth = Src->getType()->getScalarSizeInBits();
- if (Log2_32(MaxVScale) < (TypeWidth - 1)) {
+ if (MaxVScale > 0 && Log2_32(MaxVScale) < (SrcBitSize - 1)) {
Value *VScale = Builder.CreateVScale(ConstantInt::get(DestTy, 1));
return replaceInstUsesWith(CI, VScale);
}
diff --git a/llvm/test/Transforms/InstCombine/vscale_sext_and_zext.ll b/llvm/test/Transforms/InstCombine/vscale_sext_and_zext.ll
index 9ba03cb31f4df..26fa24cec3b9a 100644
--- a/llvm/test/Transforms/InstCombine/vscale_sext_and_zext.ll
+++ b/llvm/test/Transforms/InstCombine/vscale_sext_and_zext.ll
@@ -1,85 +1,109 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
-define i64 @vscale_SExt_i32toi64() #0 {
-; CHECK: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT: ret i64 [[TMP0]]
-entry:
- %0 = call i32 @llvm.vscale.i32()
- %1 = sext i32 %0 to i64
- ret i64 %1
-}
+;
+; Sign-extend
+;
-define i32 @vscale_SExt_i8toi32() #0 {
-; CHECK: entry:
+define i32 @vscale_SExt_i8toi32() vscale_range(0, 127) {
+; CHECK-LABEL: @vscale_SExt_i8toi32(
+; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-NEXT: ret i32 [[TMP0]]
+;
entry:
%0 = call i8 @llvm.vscale.i8()
%1 = sext i8 %0 to i32
ret i32 %1
}
-
-define i32 @vscale_SExt_i8toi32_poison() vscale_range(0, 192) {
-; CHECK: entry:
+define i32 @vscale_SExt_i8toi32_poison() vscale_range(0, 128) {
+; CHECK-LABEL: @vscale_SExt_i8toi32_poison(
+; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[TMP0]] to i32
; CHECK-NEXT: ret i32 [[TMP1]]
+;
entry:
%0 = call i8 @llvm.vscale.i8()
%1 = sext i8 %0 to i32
ret i32 %1
}
+;
+; Zero-extend
+;
-
-define i64 @vscale_ZExt_i32toi64() #0 {
-; CHECK: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT: ret i64 [[TMP0]]
+define i32 @vscale_ZExt_i8toi32() vscale_range(0, 128) {
+; CHECK-LABEL: @vscale_ZExt_i8toi32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
+; CHECK-NEXT: ret i32 [[TMP0]]
+;
entry:
- %0 = call i32 @llvm.vscale.i32()
- %1 = zext i32 %0 to i64
- ret i64 %1
+ %0 = call i8 @llvm.vscale.i8()
+ %1 = zext i8 %0 to i32
+ ret i32 %1
}
-define i64 @vscale_ZExt_i1toi64() vscale_range(0, 1) {
-; CHECK: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT: ret i64 [[TMP0]]
-entry:
- %0 = call i1 @llvm.vscale.i1()
- %1 = zext i1 %0 to i64
- ret i64 %1
+define i32 @vscale_ZExt_i8toi32_poison() vscale_range(0, 256) {
+; CHECK-LABEL: @vscale_ZExt_i8toi32_poison(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
+; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ entry:
+ %0 = call i8 @llvm.vscale.i8()
+ %1 = zext i8 %0 to i32
+ ret i32 %1
}
-define i32 @vscale_ZExt_i8toi32_poison() vscale_range(0, 1024) {
-; CHECK: entry:
+;
+; No vscale_range attribute
+;
+
+define i32 @vscale_ZExt_i8toi32_unknown() {
+; CHECK-LABEL: @vscale_ZExt_i8toi32_unknown(
+; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: ret i32 [[TMP1]]
+;
entry:
%0 = call i8 @llvm.vscale.i8()
%1 = zext i8 %0 to i32
ret i32 %1
}
-define i32 @vscale_ZExt_i16toi32_unknown() {
-; CHECK: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call i16 @llvm.vscale.i16()
-; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[TMP0]] to i32
+;
+; unbounded vscale_range maximum (0)
+;
+
+define i32 @vscale_SExt_i8toi32_unbounded() vscale_range(0, 0) {
+; CHECK-LABEL: @vscale_SExt_i8toi32_unbounded(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
+; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[TMP0]] to i32
; CHECK-NEXT: ret i32 [[TMP1]]
+;
entry:
- %0 = call i16 @llvm.vscale.i16()
- %1 = zext i16 %0 to i32
+ %0 = call i8 @llvm.vscale.i8()
+ %1 = sext i8 %0 to i32
ret i32 %1
}
-attributes #0 = { vscale_range(0, 16) }
+define i32 @vscale_ZExt_i8toi32_unbounded() vscale_range(0, 0) {
+; CHECK-LABEL: @vscale_ZExt_i8toi32_unbounded(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = call i8 @llvm.vscale.i8()
+; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
+; CHECK-NEXT: ret i32 [[TMP1]]
+;
+ entry:
+ %0 = call i8 @llvm.vscale.i8()
+ %1 = zext i8 %0 to i32
+ ret i32 %1
+}
-declare i1 @llvm.vscale.i1()
declare i8 @llvm.vscale.i8()
-declare i16 @llvm.vscale.i16()
-declare i32 @llvm.vscale.i32()
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