[PATCH] D106449: [amdgpu] Handle the case where there is no scavenged register.

[Michael Liao via Phabricator via llvm-commits]

hliao updated this revision to Diff 364125.
hliao added a comment.

Rebase and kindly PING for review.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106449/new/

https://reviews.llvm.org/D106449

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/BranchRelaxation.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/AVR/AVRInstrInfo.cpp
  llvm/lib/Target/AVR/AVRInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll

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