[PATCH] D107432: [RISCV] Emit DWARF location expression for RVV stack objects.

[Hsiangkai Wang via Phabricator via llvm-commits]

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VLENB is the length of a vector register in bytes. We use
<vscale x 64 bits> to represent one vector register. The dwarf offset is
VLENB * scalable_offset / 8.

For the mask vector, it occupies one vector register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107432

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir

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