[llvm] f0658c7 - [MCA][NFC] Add tests for PR51318 and PR51322.
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 3 09:07:27 PDT 2021
Author: Andrea Di Biagio
Date: 2021-08-03T17:06:34+01:00
New Revision: f0658c7a429b9e356da1670b280ab943ad0b0b94
URL: https://github.com/llvm/llvm-project/commit/f0658c7a429b9e356da1670b280ab943ad0b0b94
DIFF: https://github.com/llvm/llvm-project/commit/f0658c7a429b9e356da1670b280ab943ad0b0b94.diff
LOG: [MCA][NFC] Add tests for PR51318 and PR51322.
Also, regenerate existing X86 tests using update_mca_test.py.
Added:
llvm/test/tools/llvm-mca/X86/BtVer2/adc-sequence-readadvance.s
llvm/test/tools/llvm-mca/X86/BtVer2/rmw-adc-sequence-readadvance.s
llvm/test/tools/llvm-mca/X86/BtVer2/rmw-add-sequence-readadvance.s
Modified:
llvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s
llvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s
llvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s
llvm/test/tools/llvm-mca/X86/BdVer2/load-store-throughput.s
llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s
llvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s
llvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s
llvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s
llvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s
llvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s
llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s
llvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s
llvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s
llvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s
llvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s
llvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s
llvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s
llvm/test/tools/llvm-mca/X86/option-all-stats-1.s
llvm/test/tools/llvm-mca/X86/option-all-stats-2.s
llvm/test/tools/llvm-mca/X86/option-all-views-1.s
llvm/test/tools/llvm-mca/X86/option-all-views-2.s
Removed:
################################################################################
diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s b/llvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s
index b600e387459fb..97649581c2192 100644
--- a/llvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s
+++ b/llvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s
@@ -76,6 +76,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -172,6 +173,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -268,6 +270,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -364,6 +367,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -460,6 +464,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -556,6 +561,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s b/llvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s
index 558e91d439738..1e1bfd5c98ca6 100644
--- a/llvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s
+++ b/llvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s
@@ -76,6 +76,7 @@ movaps (%rbx), %xmm3
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -172,6 +173,7 @@ movaps (%rbx), %xmm3
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -268,6 +270,7 @@ movaps (%rbx), %xmm3
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -364,6 +367,7 @@ movaps (%rbx), %xmm3
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -460,6 +464,7 @@ movaps (%rbx), %xmm3
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -556,6 +561,7 @@ movaps (%rbx), %xmm3
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s b/llvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s
index 7d1fb6c246309..259a478ddd1e1 100644
--- a/llvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s
+++ b/llvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s
@@ -76,6 +76,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -173,6 +174,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -270,6 +272,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -367,6 +370,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -464,6 +468,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -561,6 +566,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/load-store-throughput.s b/llvm/test/tools/llvm-mca/X86/BdVer2/load-store-throughput.s
index 4b8f9e7e06cda..a7fbb2352c737 100644
--- a/llvm/test/tools/llvm-mca/X86/BdVer2/load-store-throughput.s
+++ b/llvm/test/tools/llvm-mca/X86/BdVer2/load-store-throughput.s
@@ -76,6 +76,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -193,6 +194,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -310,6 +312,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -427,6 +430,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -544,6 +548,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 432 (78.1%)
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -661,6 +666,7 @@ movaps %xmm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s b/llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s
index 49560697379b9..60566b7119f57 100644
--- a/llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s
+++ b/llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s
@@ -83,6 +83,7 @@ vmovaps (%rbx), %ymm3
# CHECK-NEXT: LQ - Load queue full: 354 (87.2%)
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -197,6 +198,7 @@ vmovaps (%rbx), %ymm3
# CHECK-NEXT: LQ - Load queue full: 354 (87.2%)
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -311,6 +313,7 @@ vmovaps (%rbx), %ymm3
# CHECK-NEXT: LQ - Load queue full: 354 (87.2%)
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -425,6 +428,7 @@ vmovaps (%rbx), %ymm3
# CHECK-NEXT: LQ - Load queue full: 354 (87.2%)
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -539,6 +543,7 @@ vmovaps (%rbx), %ymm3
# CHECK-NEXT: LQ - Load queue full: 533 (88.1%)
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -654,6 +659,7 @@ vmovaps (%rbx), %ymm3
# CHECK-NEXT: LQ - Load queue full: 533 (88.1%)
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -769,6 +775,7 @@ vmovaps (%rbx), %ymm3
# CHECK-NEXT: LQ - Load queue full: 345 (57.0%)
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s
index b93ee5c09d7fc..eb9f3e6194e4c 100644
--- a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s
+++ b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s
@@ -21,6 +21,7 @@ vmulps %xmm0, %xmm0, %xmm0
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s
index c68b610049fd3..f7a6bfaebe5eb 100644
--- a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s
+++ b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s
@@ -21,6 +21,7 @@ vmulps %xmm0, %xmm0, %xmm0
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s
index 64d5a045c3bbc..df6613cec2831 100644
--- a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s
+++ b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s
@@ -31,6 +31,7 @@ idiv %eax
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s
index 09c9e4af7e0c5..10d3859062c0b 100644
--- a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s
+++ b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s
@@ -31,6 +31,7 @@ idiv %eax
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s
index 6c86b6ebe2238..465e904abd3ed 100644
--- a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s
+++ b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s
@@ -52,6 +52,7 @@
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s b/llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s
index c00b1c92a544b..e7e177bc9f6a2 100644
--- a/llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s
+++ b/llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s
@@ -83,6 +83,7 @@ vmovaps %ymm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 371 (92.1%)
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -197,6 +198,7 @@ vmovaps %ymm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 371 (92.1%)
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -311,6 +313,7 @@ vmovaps %ymm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 371 (92.1%)
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -425,6 +428,7 @@ vmovaps %ymm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 371 (92.1%)
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -539,6 +543,7 @@ vmovaps %ymm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 748 (93.2%)
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -655,6 +660,7 @@ vmovaps %ymm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 559 (92.9%)
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
@@ -770,6 +776,7 @@ vmovaps %ymm3, (%rbx)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 561 (7.8%)
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/adc-sequence-readadvance.s b/llvm/test/tools/llvm-mca/X86/BtVer2/adc-sequence-readadvance.s
new file mode 100644
index 0000000000000..68537e4f76746
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/BtVer2/adc-sequence-readadvance.s
@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=4 -timeline < %s | FileCheck %s
+
+# FIXME: PR51318
+# Missing read-advance for the implicit use of register EFLAGS.
+
+adc 4(%rsp), %eax
+
+# CHECK: Iterations: 4
+# CHECK-NEXT: Instructions: 4
+# CHECK-NEXT: Total Cycles: 19
+# CHECK-NEXT: Total uOps: 4
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 0.21
+# CHECK-NEXT: IPC: 0.21
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 1.00 * adcl 4(%rsp), %eax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - JALU0
+# CHECK-NEXT: [1] - JALU1
+# CHECK-NEXT: [2] - JDiv
+# CHECK-NEXT: [3] - JFPA
+# CHECK-NEXT: [4] - JFPM
+# CHECK-NEXT: [5] - JFPU0
+# CHECK-NEXT: [6] - JFPU1
+# CHECK-NEXT: [7] - JLAGU
+# CHECK-NEXT: [8] - JMul
+# CHECK-NEXT: [9] - JSAGU
+# CHECK-NEXT: [10] - JSTC
+# CHECK-NEXT: [11] - JVALU0
+# CHECK-NEXT: [12] - JVALU1
+# CHECK-NEXT: [13] - JVIMUL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
+# CHECK-NEXT: 1.00 1.00 - - - - - 1.00 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
+# CHECK-NEXT: 1.00 1.00 - - - - - 1.00 - - - - - - adcl 4(%rsp), %eax
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012345678
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . . . adcl 4(%rsp), %eax
+# CHECK-NEXT: [1,0] D====eeeeER . . adcl 4(%rsp), %eax
+# CHECK-NEXT: [2,0] .D=======eeeeER. . adcl 4(%rsp), %eax
+# CHECK-NEXT: [3,0] .D===========eeeeER adcl 4(%rsp), %eax
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 4 6.5 0.3 0.0 adcl 4(%rsp), %eax
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s
index 1492de0c7ff4a..2eb6dee5e99d7 100644
--- a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s
+++ b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-1.s
@@ -21,6 +21,7 @@ vmulps %xmm0, %xmm0, %xmm0
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s
index ba33ba065ff06..66541f9e7fad2 100644
--- a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s
+++ b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-2.s
@@ -21,6 +21,7 @@ vmulps %xmm0, %xmm0, %xmm0
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s
index 342f122d66bb8..94a40ca24eb5c 100644
--- a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s
+++ b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-3.s
@@ -31,6 +31,7 @@ idiv %eax
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s
index 6dfb87f15be41..9e95042dcb5d9 100644
--- a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s
+++ b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-4.s
@@ -31,6 +31,7 @@ idiv %eax
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s
index 32101c718d538..a372b5713eb52 100644
--- a/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s
+++ b/llvm/test/tools/llvm-mca/X86/BtVer2/register-files-5.s
@@ -52,6 +52,7 @@
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/rmw-adc-sequence-readadvance.s b/llvm/test/tools/llvm-mca/X86/BtVer2/rmw-adc-sequence-readadvance.s
new file mode 100644
index 0000000000000..16387c6c26e95
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/BtVer2/rmw-adc-sequence-readadvance.s
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline < %s | FileCheck %s
+
+# FIXME: PR51322
+# Missing read-advance for register EAX.
+
+add %eax, %eax
+adc %eax, 4(%rsp)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 2
+# CHECK-NEXT: Total Cycles: 10
+# CHECK-NEXT: Total uOps: 2
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 0.20
+# CHECK-NEXT: IPC: 0.20
+# CHECK-NEXT: Block RThroughput: 1.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 addl %eax, %eax
+# CHECK-NEXT: 1 6 1.00 * * adcl %eax, 4(%rsp)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - JALU0
+# CHECK-NEXT: [1] - JALU1
+# CHECK-NEXT: [2] - JDiv
+# CHECK-NEXT: [3] - JFPA
+# CHECK-NEXT: [4] - JFPM
+# CHECK-NEXT: [5] - JFPU0
+# CHECK-NEXT: [6] - JFPU1
+# CHECK-NEXT: [7] - JLAGU
+# CHECK-NEXT: [8] - JMul
+# CHECK-NEXT: [9] - JSAGU
+# CHECK-NEXT: [10] - JSTC
+# CHECK-NEXT: [11] - JVALU0
+# CHECK-NEXT: [12] - JVALU1
+# CHECK-NEXT: [13] - JVIMUL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
+# CHECK-NEXT: 2.00 1.00 - - - - - 1.00 - 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - addl %eax, %eax
+# CHECK-NEXT: 2.00 - - - - - - 1.00 - 1.00 - - - - adcl %eax, 4(%rsp)
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeER . . addl %eax, %eax
+# CHECK-NEXT: [0,1] D=eeeeeeER adcl %eax, 4(%rsp)
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 addl %eax, %eax
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 adcl %eax, 4(%rsp)
+# CHECK-NEXT: 1 1.5 0.5 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/rmw-add-sequence-readadvance.s b/llvm/test/tools/llvm-mca/X86/BtVer2/rmw-add-sequence-readadvance.s
new file mode 100644
index 0000000000000..7ff8884da8522
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/BtVer2/rmw-add-sequence-readadvance.s
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline < %s | FileCheck %s
+
+# FIXME: PR51322
+# Missing read-advance for register EAX.
+
+add %eax, %eax
+add %eax, 4(%rsp)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 2
+# CHECK-NEXT: Total Cycles: 10
+# CHECK-NEXT: Total uOps: 2
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 0.20
+# CHECK-NEXT: IPC: 0.20
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 addl %eax, %eax
+# CHECK-NEXT: 1 6 1.00 * * addl %eax, 4(%rsp)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - JALU0
+# CHECK-NEXT: [1] - JALU1
+# CHECK-NEXT: [2] - JDiv
+# CHECK-NEXT: [3] - JFPA
+# CHECK-NEXT: [4] - JFPM
+# CHECK-NEXT: [5] - JFPU0
+# CHECK-NEXT: [6] - JFPU1
+# CHECK-NEXT: [7] - JLAGU
+# CHECK-NEXT: [8] - JMul
+# CHECK-NEXT: [9] - JSAGU
+# CHECK-NEXT: [10] - JSTC
+# CHECK-NEXT: [11] - JVALU0
+# CHECK-NEXT: [12] - JVALU1
+# CHECK-NEXT: [13] - JVIMUL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
+# CHECK-NEXT: 1.00 1.00 - - - - - 1.00 - 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - addl %eax, %eax
+# CHECK-NEXT: 1.00 - - - - - - 1.00 - 1.00 - - - - addl %eax, 4(%rsp)
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeER . . addl %eax, %eax
+# CHECK-NEXT: [0,1] D=eeeeeeER addl %eax, 4(%rsp)
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 addl %eax, %eax
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 addl %eax, 4(%rsp)
+# CHECK-NEXT: 1 1.5 0.5 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s b/llvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s
index f0a0567a682e3..7bd095670d671 100644
--- a/llvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s
+++ b/llvm/test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s
@@ -31,6 +31,7 @@ cmpxchg16b (%rsi)
# CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/option-all-stats-1.s b/llvm/test/tools/llvm-mca/X86/option-all-stats-1.s
index dbd315284f266..21476d05eae52 100644
--- a/llvm/test/tools/llvm-mca/X86/option-all-stats-1.s
+++ b/llvm/test/tools/llvm-mca/X86/option-all-stats-1.s
@@ -34,6 +34,7 @@ add %eax, %eax
# FULLREPORT-NEXT: LQ - Load queue full: 0
# FULLREPORT-NEXT: SQ - Store queue full: 0
# FULLREPORT-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# FULLREPORT-NEXT: USH - Uncategorised Structural Hazard: 0
# FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# FULLREPORT-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/option-all-stats-2.s b/llvm/test/tools/llvm-mca/X86/option-all-stats-2.s
index 49b50a7f5296f..e93ba262a9f9d 100644
--- a/llvm/test/tools/llvm-mca/X86/option-all-stats-2.s
+++ b/llvm/test/tools/llvm-mca/X86/option-all-stats-2.s
@@ -35,6 +35,7 @@ add %eax, %eax
# FULL-NEXT: LQ - Load queue full: 0
# FULL-NEXT: SQ - Store queue full: 0
# FULL-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# FULL-NEXT: USH - Uncategorised Structural Hazard: 0
# FULL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# FULL-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/option-all-views-1.s b/llvm/test/tools/llvm-mca/X86/option-all-views-1.s
index 6b82e5e4f86a2..c8a108882d1e8 100644
--- a/llvm/test/tools/llvm-mca/X86/option-all-views-1.s
+++ b/llvm/test/tools/llvm-mca/X86/option-all-views-1.s
@@ -56,6 +56,7 @@ add %eax, %eax
# FULLREPORT-NEXT: LQ - Load queue full: 0
# FULLREPORT-NEXT: SQ - Store queue full: 0
# FULLREPORT-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# FULLREPORT-NEXT: USH - Uncategorised Structural Hazard: 0
# FULLREPORT: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# FULLREPORT-NEXT: [# dispatched], [# cycles]
diff --git a/llvm/test/tools/llvm-mca/X86/option-all-views-2.s b/llvm/test/tools/llvm-mca/X86/option-all-views-2.s
index 2d3e746fed7ec..6c7ba1666b7bc 100644
--- a/llvm/test/tools/llvm-mca/X86/option-all-views-2.s
+++ b/llvm/test/tools/llvm-mca/X86/option-all-views-2.s
@@ -55,6 +55,7 @@ add %eax, %eax
# ALL-NEXT: LQ - Load queue full: 0
# ALL-NEXT: SQ - Store queue full: 0
# ALL-NEXT: GROUP - Static restrictions on the dispatch group: 0
+# ALL-NEXT: USH - Uncategorised Structural Hazard: 0
# ALL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# ALL-NEXT: [# dispatched], [# cycles]
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