[PATCH] D107057: [llvm][sve] Lowering for VLS extending loads

[Bradley Smith via Phabricator via llvm-commits]

bsmith added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll:50-63
+
+  ; Ensure sensible type legalistaion
+  ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16
+  ; VBITS_EQ_256-DAG: ld1h { [[Z0:z[0-9]+]].h }, [[PG]]/z, [x0]
+  ; VBITS_EQ_256-DAG: mov x9, sp
+  ; VBITS_EQ_256-DAG: st1h { [[Z0]].h }, [[PG]], [x9]
+  ; VBITS_EQ_256-DAG: ldp q[[R0:[0-9]+]], q[[R1:[0-9]+]], [sp]
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The codegen in the type legalisation cases seems a bit odd, why is this not using SVE to do the extending load?


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107057/new/

https://reviews.llvm.org/D107057