[llvm] 739efad - [AArch64] Regenerate fp16 tests.
Eli Friedman via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 2 13:05:56 PDT 2021
Author: Eli Friedman
Date: 2021-08-02T13:05:16-07:00
New Revision: 739efad3f6e36282b7d3a4c76802424473249b41
URL: https://github.com/llvm/llvm-project/commit/739efad3f6e36282b7d3a4c76802424473249b41
DIFF: https://github.com/llvm/llvm-project/commit/739efad3f6e36282b7d3a4c76802424473249b41.diff
LOG: [AArch64] Regenerate fp16 tests.
Added:
Modified:
llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll
llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll
index eafc5d9df7fb..af3b52f66de7 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll
@@ -1,18 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
define <16 x half> @sitofp_i32(<16 x i32> %a) #0 {
; CHECK-LABEL: sitofp_i32:
-; CHECK-DAG: scvtf [[S0:v[0-9]+\.4s]], v0.4s
-; CHECK-DAG: scvtf [[S1:v[0-9]+\.4s]], v1.4s
-; CHECK-DAG: scvtf [[S2:v[0-9]+\.4s]], v2.4s
-; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s
-; CHECK-DAG: fcvtn v0.4h, [[S0]]
-; CHECK-DAG: fcvtn v1.4h, [[S2]]
-; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
-; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
-; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf v1.4s, v1.4s
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: scvtf v3.4s, v3.4s
+; CHECK-NEXT: scvtf v2.4s, v2.4s
+; CHECK-NEXT: fcvtn v4.4h, v1.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-NEXT: fcvtn v1.4h, v2.4s
+; CHECK-NEXT: mov v0.d[1], v4.d[0]
+; CHECK-NEXT: mov v1.d[1], v3.d[0]
+; CHECK-NEXT: ret
%1 = sitofp <16 x i32> %a to <16 x half>
ret <16 x half> %1
@@ -21,31 +24,33 @@ define <16 x half> @sitofp_i32(<16 x i32> %a) #0 {
define <16 x half> @sitofp_i64(<16 x i64> %a) #0 {
; CHECK-LABEL: sitofp_i64:
-; CHECK-DAG: scvtf [[D0:v[0-9]+\.2d]], v0.2d
-; CHECK-DAG: scvtf [[D1:v[0-9]+\.2d]], v1.2d
-; CHECK-DAG: scvtf [[D2:v[0-9]+\.2d]], v2.2d
-; CHECK-DAG: scvtf [[D3:v[0-9]+\.2d]], v3.2d
-; CHECK-DAG: scvtf [[D4:v[0-9]+\.2d]], v4.2d
-; CHECK-DAG: scvtf [[D5:v[0-9]+\.2d]], v5.2d
-; CHECK-DAG: scvtf [[D6:v[0-9]+\.2d]], v6.2d
-; CHECK-DAG: scvtf [[D7:v[0-9]+\.2d]], v7.2d
-
-; CHECK-DAG: fcvtn [[S0:v[0-9]+]].2s, [[D0]]
-; CHECK-DAG: fcvtn [[S1:v[0-9]+]].2s, [[D2]]
-; CHECK-DAG: fcvtn [[S2:v[0-9]+]].2s, [[D4]]
-; CHECK-DAG: fcvtn [[S3:v[0-9]+]].2s, [[D6]]
-
-; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
-; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
-; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
-; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
-
-; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
-; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
-; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
-; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
-; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf v2.2d, v2.2d
+; CHECK-NEXT: scvtf v0.2d, v0.2d
+; CHECK-NEXT: scvtf v6.2d, v6.2d
+; CHECK-NEXT: scvtf v4.2d, v4.2d
+; CHECK-NEXT: scvtf v3.2d, v3.2d
+; CHECK-NEXT: scvtf v1.2d, v1.2d
+; CHECK-NEXT: scvtf v7.2d, v7.2d
+; CHECK-NEXT: scvtf v5.2d, v5.2d
+; CHECK-NEXT: fcvtn v2.2s, v2.2d
+; CHECK-NEXT: fcvtn v0.2s, v0.2d
+; CHECK-NEXT: fcvtn v6.2s, v6.2d
+; CHECK-NEXT: fcvtn v4.2s, v4.2d
+; CHECK-NEXT: fcvtn2 v2.4s, v3.2d
+; CHECK-NEXT: fcvtn2 v0.4s, v1.2d
+; CHECK-NEXT: fcvtn2 v6.4s, v7.2d
+; CHECK-NEXT: fcvtn2 v4.4s, v5.2d
+; CHECK-NEXT: fcvtn v2.4h, v2.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: fcvtn v3.4h, v6.4s
+; CHECK-NEXT: fcvtn v1.4h, v4.4s
+; CHECK-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-NEXT: mov v1.d[1], v3.d[0]
+; CHECK-NEXT: ret
+
+
+
%1 = sitofp <16 x i64> %a to <16 x half>
ret <16 x half> %1
@@ -54,16 +59,18 @@ define <16 x half> @sitofp_i64(<16 x i64> %a) #0 {
define <16 x half> @uitofp_i32(<16 x i32> %a) #0 {
; CHECK-LABEL: uitofp_i32:
-; CHECK-DAG: ucvtf [[S0:v[0-9]+\.4s]], v0.4s
-; CHECK-DAG: ucvtf [[S1:v[0-9]+\.4s]], v1.4s
-; CHECK-DAG: ucvtf [[S2:v[0-9]+\.4s]], v2.4s
-; CHECK-DAG: ucvtf [[S3:v[0-9]+\.4s]], v3.4s
-; CHECK-DAG: fcvtn v0.4h, [[S0]]
-; CHECK-DAG: fcvtn v1.4h, [[S2]]
-; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
-; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
-; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf v1.4s, v1.4s
+; CHECK-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-NEXT: ucvtf v3.4s, v3.4s
+; CHECK-NEXT: ucvtf v2.4s, v2.4s
+; CHECK-NEXT: fcvtn v4.4h, v1.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: fcvtn v3.4h, v3.4s
+; CHECK-NEXT: fcvtn v1.4h, v2.4s
+; CHECK-NEXT: mov v0.d[1], v4.d[0]
+; CHECK-NEXT: mov v1.d[1], v3.d[0]
+; CHECK-NEXT: ret
%1 = uitofp <16 x i32> %a to <16 x half>
ret <16 x half> %1
@@ -72,31 +79,33 @@ define <16 x half> @uitofp_i32(<16 x i32> %a) #0 {
define <16 x half> @uitofp_i64(<16 x i64> %a) #0 {
; CHECK-LABEL: uitofp_i64:
-; CHECK-DAG: ucvtf [[D0:v[0-9]+\.2d]], v0.2d
-; CHECK-DAG: ucvtf [[D1:v[0-9]+\.2d]], v1.2d
-; CHECK-DAG: ucvtf [[D2:v[0-9]+\.2d]], v2.2d
-; CHECK-DAG: ucvtf [[D3:v[0-9]+\.2d]], v3.2d
-; CHECK-DAG: ucvtf [[D4:v[0-9]+\.2d]], v4.2d
-; CHECK-DAG: ucvtf [[D5:v[0-9]+\.2d]], v5.2d
-; CHECK-DAG: ucvtf [[D6:v[0-9]+\.2d]], v6.2d
-; CHECK-DAG: ucvtf [[D7:v[0-9]+\.2d]], v7.2d
-
-; CHECK-DAG: fcvtn [[S0:v[0-9]+]].2s, [[D0]]
-; CHECK-DAG: fcvtn [[S1:v[0-9]+]].2s, [[D2]]
-; CHECK-DAG: fcvtn [[S2:v[0-9]+]].2s, [[D4]]
-; CHECK-DAG: fcvtn [[S3:v[0-9]+]].2s, [[D6]]
-
-; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
-; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
-; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
-; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
-
-; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
-; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
-; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
-; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
-; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]
-; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf v2.2d, v2.2d
+; CHECK-NEXT: ucvtf v0.2d, v0.2d
+; CHECK-NEXT: ucvtf v6.2d, v6.2d
+; CHECK-NEXT: ucvtf v4.2d, v4.2d
+; CHECK-NEXT: ucvtf v3.2d, v3.2d
+; CHECK-NEXT: ucvtf v1.2d, v1.2d
+; CHECK-NEXT: ucvtf v7.2d, v7.2d
+; CHECK-NEXT: ucvtf v5.2d, v5.2d
+; CHECK-NEXT: fcvtn v2.2s, v2.2d
+; CHECK-NEXT: fcvtn v0.2s, v0.2d
+; CHECK-NEXT: fcvtn v6.2s, v6.2d
+; CHECK-NEXT: fcvtn v4.2s, v4.2d
+; CHECK-NEXT: fcvtn2 v2.4s, v3.2d
+; CHECK-NEXT: fcvtn2 v0.4s, v1.2d
+; CHECK-NEXT: fcvtn2 v6.4s, v7.2d
+; CHECK-NEXT: fcvtn2 v4.4s, v5.2d
+; CHECK-NEXT: fcvtn v2.4h, v2.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: fcvtn v3.4h, v6.4s
+; CHECK-NEXT: fcvtn v1.4h, v4.4s
+; CHECK-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-NEXT: mov v1.d[1], v3.d[0]
+; CHECK-NEXT: ret
+
+
+
%1 = uitofp <16 x i64> %a to <16 x half>
ret <16 x half> %1
diff --git a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
index bb2b450d173a..e0c7f0c3815b 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
@@ -1,263 +1,372 @@
-; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK-CVT --check-prefix=CHECK
-; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK-FP16 --check-prefix=CHECK
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
+; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) {
-entry:
; CHECK-CVT-LABEL: add_h:
-; CHECK-CVT: fcvt
-; CHECK-CVT: fcvt
-; CHECK-CVT-DAG: fadd
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fadd
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fadd
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fadd
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fadd
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fadd
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fadd
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fadd
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT: fcvt
-
+; CHECK-CVT: // %bb.0: // %entry
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: mov h6, v1.h[2]
+; CHECK-CVT-NEXT: mov h7, v0.h[2]
+; CHECK-CVT-NEXT: mov h16, v1.h[3]
+; CHECK-CVT-NEXT: mov h17, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcvt s5, h0
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s6, h6
+; CHECK-CVT-NEXT: fcvt s7, h7
+; CHECK-CVT-NEXT: fcvt s16, h16
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: fadd s4, s5, s4
+; CHECK-CVT-NEXT: mov h5, v1.h[4]
+; CHECK-CVT-NEXT: fadd s2, s3, s2
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fadd s6, s7, s6
+; CHECK-CVT-NEXT: mov h7, v1.h[5]
+; CHECK-CVT-NEXT: fadd s16, s17, s16
+; CHECK-CVT-NEXT: mov h17, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s5, h5
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s7, h7
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: fadd s3, s3, s5
+; CHECK-CVT-NEXT: mov h5, v1.h[6]
+; CHECK-CVT-NEXT: fadd s7, s17, s7
+; CHECK-CVT-NEXT: mov h17, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fadd s1, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s4
+; CHECK-CVT-NEXT: fcvt h2, s2
+; CHECK-CVT-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s6
+; CHECK-CVT-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s16
+; CHECK-CVT-NEXT: fcvt s5, h5
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: mov v0.h[3], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s3
+; CHECK-CVT-NEXT: fadd s5, s17, s5
+; CHECK-CVT-NEXT: fcvt h3, s7
+; CHECK-CVT-NEXT: mov v0.h[4], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h4, s5
+; CHECK-CVT-NEXT: mov v0.h[5], v3.h[0]
+; CHECK-CVT-NEXT: mov v0.h[6], v4.h[0]
+; CHECK-CVT-NEXT: fcvt h1, s1
+; CHECK-CVT-NEXT: mov v0.h[7], v1.h[0]
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: add_h:
-; CHECK-FP16: fadd v0.8h, v0.8h, v1.8h
-; CHECK-FP16-NEXT: ret
-
+; CHECK-FP16: // %bb.0: // %entry
+; CHECK-FP16-NEXT: fadd v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: ret
+entry:
%0 = fadd <8 x half> %a, %b
ret <8 x half> %0
}
define <8 x half> @sub_h(<8 x half> %a, <8 x half> %b) {
-entry:
; CHECK-CVT-LABEL: sub_h:
-; CHECK-CVT: fcvt
-; CHECK-CVT: fcvt
-; CHECK-CVT-DAG: fsub
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fsub
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fsub
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fsub
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fsub
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fsub
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fsub
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fsub
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT: fcvt
-
+; CHECK-CVT: // %bb.0: // %entry
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: mov h6, v1.h[2]
+; CHECK-CVT-NEXT: mov h7, v0.h[2]
+; CHECK-CVT-NEXT: mov h16, v1.h[3]
+; CHECK-CVT-NEXT: mov h17, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcvt s5, h0
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s6, h6
+; CHECK-CVT-NEXT: fcvt s7, h7
+; CHECK-CVT-NEXT: fcvt s16, h16
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: fsub s4, s5, s4
+; CHECK-CVT-NEXT: mov h5, v1.h[4]
+; CHECK-CVT-NEXT: fsub s2, s3, s2
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fsub s6, s7, s6
+; CHECK-CVT-NEXT: mov h7, v1.h[5]
+; CHECK-CVT-NEXT: fsub s16, s17, s16
+; CHECK-CVT-NEXT: mov h17, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s5, h5
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s7, h7
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: fsub s3, s3, s5
+; CHECK-CVT-NEXT: mov h5, v1.h[6]
+; CHECK-CVT-NEXT: fsub s7, s17, s7
+; CHECK-CVT-NEXT: mov h17, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fsub s1, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s4
+; CHECK-CVT-NEXT: fcvt h2, s2
+; CHECK-CVT-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s6
+; CHECK-CVT-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s16
+; CHECK-CVT-NEXT: fcvt s5, h5
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: mov v0.h[3], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s3
+; CHECK-CVT-NEXT: fsub s5, s17, s5
+; CHECK-CVT-NEXT: fcvt h3, s7
+; CHECK-CVT-NEXT: mov v0.h[4], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h4, s5
+; CHECK-CVT-NEXT: mov v0.h[5], v3.h[0]
+; CHECK-CVT-NEXT: mov v0.h[6], v4.h[0]
+; CHECK-CVT-NEXT: fcvt h1, s1
+; CHECK-CVT-NEXT: mov v0.h[7], v1.h[0]
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: sub_h:
-; CHECK-FP16: fsub v0.8h, v0.8h, v1.8h
-; CHECK-FP16-NEXT: ret
-
+; CHECK-FP16: // %bb.0: // %entry
+; CHECK-FP16-NEXT: fsub v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: ret
+entry:
%0 = fsub <8 x half> %a, %b
ret <8 x half> %0
}
define <8 x half> @mul_h(<8 x half> %a, <8 x half> %b) {
-entry:
; CHECK-CVT-LABEL: mul_h:
-; CHECK-CVT: fcvt
-; CHECK-CVT: fcvt
-; CHECK-CVT-DAG: fmul
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fmul
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fmul
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fmul
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fmul
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fmul
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fmul
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fmul
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT: fcvt
-
+; CHECK-CVT: // %bb.0: // %entry
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: mov h6, v1.h[2]
+; CHECK-CVT-NEXT: mov h7, v0.h[2]
+; CHECK-CVT-NEXT: mov h16, v1.h[3]
+; CHECK-CVT-NEXT: mov h17, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcvt s5, h0
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s6, h6
+; CHECK-CVT-NEXT: fcvt s7, h7
+; CHECK-CVT-NEXT: fcvt s16, h16
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: fmul s4, s5, s4
+; CHECK-CVT-NEXT: mov h5, v1.h[4]
+; CHECK-CVT-NEXT: fmul s2, s3, s2
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fmul s6, s7, s6
+; CHECK-CVT-NEXT: mov h7, v1.h[5]
+; CHECK-CVT-NEXT: fmul s16, s17, s16
+; CHECK-CVT-NEXT: mov h17, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s5, h5
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s7, h7
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: fmul s3, s3, s5
+; CHECK-CVT-NEXT: mov h5, v1.h[6]
+; CHECK-CVT-NEXT: fmul s7, s17, s7
+; CHECK-CVT-NEXT: mov h17, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fmul s1, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s4
+; CHECK-CVT-NEXT: fcvt h2, s2
+; CHECK-CVT-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s6
+; CHECK-CVT-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s16
+; CHECK-CVT-NEXT: fcvt s5, h5
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: mov v0.h[3], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s3
+; CHECK-CVT-NEXT: fmul s5, s17, s5
+; CHECK-CVT-NEXT: fcvt h3, s7
+; CHECK-CVT-NEXT: mov v0.h[4], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h4, s5
+; CHECK-CVT-NEXT: mov v0.h[5], v3.h[0]
+; CHECK-CVT-NEXT: mov v0.h[6], v4.h[0]
+; CHECK-CVT-NEXT: fcvt h1, s1
+; CHECK-CVT-NEXT: mov v0.h[7], v1.h[0]
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: mul_h:
-; CHECK-FP16: fmul v0.8h, v0.8h, v1.8h
-; CHECK-FP16-NEXT: ret
-
+; CHECK-FP16: // %bb.0: // %entry
+; CHECK-FP16-NEXT: fmul v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: ret
+entry:
%0 = fmul <8 x half> %a, %b
ret <8 x half> %0
}
define <8 x half> @div_h(<8 x half> %a, <8 x half> %b) {
-entry:
; CHECK-CVT-LABEL: div_h:
-; CHECK-CVT: fcvt
-; CHECK-CVT: fcvt
-; CHECK-CVT-DAG: fdiv
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fdiv
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fdiv
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fdiv
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fdiv
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fdiv
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fdiv
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fdiv
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT: fcvt
-
+; CHECK-CVT: // %bb.0: // %entry
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: mov h6, v1.h[2]
+; CHECK-CVT-NEXT: mov h7, v0.h[2]
+; CHECK-CVT-NEXT: mov h16, v1.h[3]
+; CHECK-CVT-NEXT: mov h17, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcvt s5, h0
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s6, h6
+; CHECK-CVT-NEXT: fcvt s7, h7
+; CHECK-CVT-NEXT: fcvt s16, h16
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: fdiv s4, s5, s4
+; CHECK-CVT-NEXT: mov h5, v1.h[4]
+; CHECK-CVT-NEXT: fdiv s2, s3, s2
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fdiv s6, s7, s6
+; CHECK-CVT-NEXT: mov h7, v1.h[5]
+; CHECK-CVT-NEXT: fdiv s16, s17, s16
+; CHECK-CVT-NEXT: mov h17, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s5, h5
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s7, h7
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: fdiv s3, s3, s5
+; CHECK-CVT-NEXT: mov h5, v1.h[6]
+; CHECK-CVT-NEXT: fdiv s7, s17, s7
+; CHECK-CVT-NEXT: mov h17, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: fdiv s1, s0, s1
+; CHECK-CVT-NEXT: fcvt h0, s4
+; CHECK-CVT-NEXT: fcvt h2, s2
+; CHECK-CVT-NEXT: mov v0.h[1], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s6
+; CHECK-CVT-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s16
+; CHECK-CVT-NEXT: fcvt s5, h5
+; CHECK-CVT-NEXT: fcvt s17, h17
+; CHECK-CVT-NEXT: mov v0.h[3], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h2, s3
+; CHECK-CVT-NEXT: fdiv s5, s17, s5
+; CHECK-CVT-NEXT: fcvt h3, s7
+; CHECK-CVT-NEXT: mov v0.h[4], v2.h[0]
+; CHECK-CVT-NEXT: fcvt h4, s5
+; CHECK-CVT-NEXT: mov v0.h[5], v3.h[0]
+; CHECK-CVT-NEXT: mov v0.h[6], v4.h[0]
+; CHECK-CVT-NEXT: fcvt h1, s1
+; CHECK-CVT-NEXT: mov v0.h[7], v1.h[0]
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: div_h:
-; CHECK-FP16: fdiv v0.8h, v0.8h, v1.8h
-; CHECK-FP16-NEXT: ret
-
+; CHECK-FP16: // %bb.0: // %entry
+; CHECK-FP16-NEXT: fdiv v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: ret
+entry:
%0 = fdiv <8 x half> %a, %b
ret <8 x half> %0
}
define <8 x half> @load_h(<8 x half>* %a) {
-entry:
; CHECK-LABEL: load_h:
-; CHECK: ldr q0, [x0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ret
+entry:
%0 = load <8 x half>, <8 x half>* %a, align 4
ret <8 x half> %0
}
define void @store_h(<8 x half>* %a, <8 x half> %b) {
-entry:
; CHECK-LABEL: store_h:
-; CHECK: str q0, [x0]
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: str q0, [x0]
+; CHECK-NEXT: ret
+entry:
store <8 x half> %b, <8 x half>* %a, align 4
ret void
}
define <8 x half> @s_to_h(<8 x float> %a) {
; CHECK-LABEL: s_to_h:
-; CHECK-DAG: fcvtn v0.4h, v0.4s
-; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s
-; CHECK: mov v0.d[1], [[REG]].d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
%1 = fptrunc <8 x float> %a to <8 x half>
ret <8 x half> %1
}
define <8 x half> @d_to_h(<8 x double> %a) {
; CHECK-LABEL: d_to_h:
-; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
-; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
-; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
-; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
-; CHECK-DAG: fcvt h
-; CHECK-DAG: fcvt h
-; CHECK-DAG: fcvt h
-; CHECK-DAG: fcvt h
-; CHECK-DAG: fcvt h
-; CHECK-DAG: fcvt h
-; CHECK-DAG: fcvt h
-; CHECK-DAG: fcvt h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
-; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov d4, v0.d[1]
+; CHECK-NEXT: fcvt h0, d0
+; CHECK-NEXT: fcvt h4, d4
+; CHECK-NEXT: mov v0.h[1], v4.h[0]
+; CHECK-NEXT: fcvt h4, d1
+; CHECK-NEXT: mov d1, v1.d[1]
+; CHECK-NEXT: mov v0.h[2], v4.h[0]
+; CHECK-NEXT: fcvt h1, d1
+; CHECK-NEXT: fcvt h4, d2
+; CHECK-NEXT: mov d2, v2.d[1]
+; CHECK-NEXT: mov v0.h[3], v1.h[0]
+; CHECK-NEXT: fcvt h2, d2
+; CHECK-NEXT: mov v0.h[4], v4.h[0]
+; CHECK-NEXT: fcvt h1, d3
+; CHECK-NEXT: mov d3, v3.d[1]
+; CHECK-NEXT: mov v0.h[5], v2.h[0]
+; CHECK-NEXT: mov v0.h[6], v1.h[0]
+; CHECK-NEXT: fcvt h1, d3
+; CHECK-NEXT: mov v0.h[7], v1.h[0]
+; CHECK-NEXT: ret
%1 = fptrunc <8 x double> %a to <8 x half>
ret <8 x half> %1
}
define <8 x float> @h_to_s(<8 x half> %a) {
; CHECK-LABEL: h_to_s:
-; CHECK: fcvtl2 v1.4s, v0.8h
-; CHECK: fcvtl v0.4s, v0.4h
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtl2 v1.4s, v0.8h
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: ret
%1 = fpext <8 x half> %a to <8 x float>
ret <8 x float> %1
}
define <8 x double> @h_to_d(<8 x half> %a) {
; CHECK-LABEL: h_to_d:
-; CHECK-DAG: mov h{{[0-9]+}}, v0.h
-; CHECK-DAG: mov h{{[0-9]+}}, v0.h
-; CHECK-DAG: mov h{{[0-9]+}}, v0.h
-; CHECK-DAG: mov h{{[0-9]+}}, v0.h
-; CHECK-DAG: mov h{{[0-9]+}}, v0.h
-; CHECK-DAG: mov h{{[0-9]+}}, v0.h
-; CHECK-DAG: mov h{{[0-9]+}}, v0.h
-; CHECK-DAG: fcvt d
-; CHECK-DAG: fcvt d
-; CHECK-DAG: fcvt d
-; CHECK-DAG: fcvt d
-; CHECK-DAG: fcvt d
-; CHECK-DAG: fcvt d
-; CHECK-DAG: fcvt d
-; CHECK-DAG: fcvt d
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov h1, v0.h[1]
+; CHECK-NEXT: fcvt d4, h0
+; CHECK-NEXT: mov h2, v0.h[3]
+; CHECK-NEXT: mov h3, v0.h[2]
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: fcvt d5, h1
+; CHECK-NEXT: fcvt d2, h2
+; CHECK-NEXT: fcvt d1, h3
+; CHECK-NEXT: mov h3, v0.h[1]
+; CHECK-NEXT: mov v1.d[1], v2.d[0]
+; CHECK-NEXT: fcvt d2, h0
+; CHECK-NEXT: fcvt d3, h3
+; CHECK-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-NEXT: mov h3, v0.h[3]
+; CHECK-NEXT: mov h0, v0.h[2]
+; CHECK-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-NEXT: fcvt d5, h3
+; CHECK-NEXT: fcvt d3, h0
+; CHECK-NEXT: mov v3.d[1], v5.d[0]
+; CHECK-NEXT: mov v0.16b, v4.16b
+; CHECK-NEXT: ret
%1 = fpext <8 x half> %a to <8 x double>
ret <8 x double> %1
}
@@ -265,14 +374,18 @@ define <8 x double> @h_to_d(<8 x half> %a) {
define <8 x half> @bitcast_i_to_h(float, <8 x i16> %a) {
; CHECK-LABEL: bitcast_i_to_h:
-; CHECK: mov v0.16b, v1.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%2 = bitcast <8 x i16> %a to <8 x half>
ret <8 x half> %2
}
define <8 x i16> @bitcast_h_to_i(float, <8 x half> %a) {
; CHECK-LABEL: bitcast_h_to_i:
-; CHECK: mov v0.16b, v1.16b
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov v0.16b, v1.16b
+; CHECK-NEXT: ret
%2 = bitcast <8 x half> %a to <8 x i16>
ret <8 x i16> %2
}
@@ -280,29 +393,37 @@ define <8 x i16> @bitcast_h_to_i(float, <8 x half> %a) {
define <8 x half> @sitofp_i8(<8 x i8> %a) #0 {
; CHECK-LABEL: sitofp_i8:
-; CHECK-NEXT: sshll v[[REG1:[0-9]+]].8h, v0.8b, #0
-; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
-; CHECK-NEXT: sshll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
-; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
-; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
-; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
-; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: mov v0.d[1], v[[LOREG]].d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-NEXT: sshll2 v1.4s, v0.8h, #0
+; CHECK-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-NEXT: scvtf v1.4s, v1.4s
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
%1 = sitofp <8 x i8> %a to <8 x half>
ret <8 x half> %1
}
define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
-; CHECK-LABEL: sitofp_i16:
-; CHECK-FP16-NEXT: scvtf v0.8h, v0.8h
-; CHECK-CVT-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
-; CHECK-CVT-NEXT: sshll [[HI:v[0-9]+\.4s]], v0.4h, #0
-; CHECK-CVT-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
-; CHECK-CVT-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
-; CHECK-CVT-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
-; CHECK-CVT-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK-CVT-NEXT: mov v0.d[1], v[[LOREG]].d[0]
+; CHECK-CVT-LABEL: sitofp_i16:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: sshll2 v1.4s, v0.8h, #0
+; CHECK-CVT-NEXT: sshll v0.4s, v0.4h, #0
+; CHECK-CVT-NEXT: scvtf v1.4s, v1.4s
+; CHECK-CVT-NEXT: scvtf v0.4s, v0.4s
+; CHECK-CVT-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-CVT-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-FP16-LABEL: sitofp_i16:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: scvtf v0.8h, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = sitofp <8 x i16> %a to <8 x half>
ret <8 x half> %1
}
@@ -310,11 +431,13 @@ define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
define <8 x half> @sitofp_i32(<8 x i32> %a) #0 {
; CHECK-LABEL: sitofp_i32:
-; CHECK-DAG: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
-; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s
-; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
-; CHECK-DAG: fcvtn v0.4h, [[OP1]]
-; CHECK: mov v0.d[1], v[[REG]].d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf v1.4s, v1.4s
+; CHECK-NEXT: scvtf v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
%1 = sitofp <8 x i32> %a to <8 x half>
ret <8 x half> %1
}
@@ -322,40 +445,56 @@ define <8 x half> @sitofp_i32(<8 x i32> %a) #0 {
define <8 x half> @sitofp_i64(<8 x i64> %a) #0 {
; CHECK-LABEL: sitofp_i64:
-; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
-; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
-; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
-; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
-; CHECK: fcvtn v0.4h, [[OP3]].4s
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf v2.2d, v2.2d
+; CHECK-NEXT: scvtf v0.2d, v0.2d
+; CHECK-NEXT: scvtf v3.2d, v3.2d
+; CHECK-NEXT: scvtf v1.2d, v1.2d
+; CHECK-NEXT: fcvtn v2.2s, v2.2d
+; CHECK-NEXT: fcvtn v0.2s, v0.2d
+; CHECK-NEXT: fcvtn2 v2.4s, v3.2d
+; CHECK-NEXT: fcvtn2 v0.4s, v1.2d
+; CHECK-NEXT: fcvtn v1.4h, v2.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
%1 = sitofp <8 x i64> %a to <8 x half>
ret <8 x half> %1
}
define <8 x half> @uitofp_i8(<8 x i8> %a) #0 {
; CHECK-LABEL: uitofp_i8:
-; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0
-; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
-; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
-; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
-; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
-; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
-; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: mov v0.d[1], v[[LOREG]].d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-NEXT: ushll2 v1.4s, v0.8h, #0
+; CHECK-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-NEXT: ucvtf v1.4s, v1.4s
+; CHECK-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
%1 = uitofp <8 x i8> %a to <8 x half>
ret <8 x half> %1
}
define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
-; CHECK-LABEL: uitofp_i16:
-; CHECK-FP16-NEXT: ucvtf v0.8h, v0.8h
-; CHECK-CVT-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
-; CHECK-CVT-NEXT: ushll [[HI:v[0-9]+\.4s]], v0.4h, #0
-; CHECK-CVT-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
-; CHECK-CVT-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
-; CHECK-CVT-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
-; CHECK-CVT-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK-CVT-NEXT: mov v0.d[1], v[[LOREG]].d[0]
+; CHECK-CVT-LABEL: uitofp_i16:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: ushll2 v1.4s, v0.8h, #0
+; CHECK-CVT-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-CVT-NEXT: ucvtf v1.4s, v1.4s
+; CHECK-CVT-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-CVT-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-CVT-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-FP16-LABEL: uitofp_i16:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: ucvtf v0.8h, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = uitofp <8 x i16> %a to <8 x half>
ret <8 x half> %1
}
@@ -363,11 +502,13 @@ define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
define <8 x half> @uitofp_i32(<8 x i32> %a) #0 {
; CHECK-LABEL: uitofp_i32:
-; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
-; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s
-; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
-; CHECK-DAG: fcvtn v0.4h, [[OP1]]
-; CHECK: mov v0.d[1], v[[REG]].d[0]
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf v1.4s, v1.4s
+; CHECK-NEXT: ucvtf v0.4s, v0.4s
+; CHECK-NEXT: fcvtn v1.4h, v1.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
%1 = uitofp <8 x i32> %a to <8 x half>
ret <8 x half> %1
}
@@ -375,43 +516,56 @@ define <8 x half> @uitofp_i32(<8 x i32> %a) #0 {
define <8 x half> @uitofp_i64(<8 x i64> %a) #0 {
; CHECK-LABEL: uitofp_i64:
-; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
-; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
-; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
-; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
-; CHECK: fcvtn v0.4h, [[OP3]].4s
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf v2.2d, v2.2d
+; CHECK-NEXT: ucvtf v0.2d, v0.2d
+; CHECK-NEXT: ucvtf v3.2d, v3.2d
+; CHECK-NEXT: ucvtf v1.2d, v1.2d
+; CHECK-NEXT: fcvtn v2.2s, v2.2d
+; CHECK-NEXT: fcvtn v0.2s, v0.2d
+; CHECK-NEXT: fcvtn2 v2.4s, v3.2d
+; CHECK-NEXT: fcvtn2 v0.4s, v1.2d
+; CHECK-NEXT: fcvtn v1.4h, v2.4s
+; CHECK-NEXT: fcvtn v0.4h, v0.4s
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
%1 = uitofp <8 x i64> %a to <8 x half>
ret <8 x half> %1
}
define void @test_insert_at_zero(half %a, <8 x half>* %b) #0 {
; CHECK-LABEL: test_insert_at_zero:
-; CHECK-NEXT: str q0, [x0]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
+; CHECK-NEXT: str q0, [x0]
+; CHECK-NEXT: ret
%1 = insertelement <8 x half> undef, half %a, i64 0
store <8 x half> %1, <8 x half>* %b, align 4
ret void
}
define <8 x i8> @fptosi_i8(<8 x half> %a) #0 {
-; CHECK-LABEL: fptosi_i8:
-; CHECK-FP16-NEXT: fcvtzs [[LO:v[0-9]+\.8h]], v0.8h
-; CHECK-CVT-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
-; CHECK-CVT-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
-; CHECK-CVT-DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]]
-; CHECK-CVT-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]]
-; CHECK-CVT-DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]]
-; CHECK-CVT-DAG: xtn2 [[I16]].8h, [[HIF32]]
-; CHECK-CVT-DAG: xtn v0.8b, [[I16]].8h
-; CHECK-FP16-NEXT: xtn v0.8b, [[LO]]
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: fptosi_i8:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-NEXT: xtn v1.4h, v1.4s
+; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-CVT-NEXT: xtn2 v1.8h, v0.4s
+; CHECK-CVT-NEXT: xtn v0.8b, v1.8h
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-FP16-LABEL: fptosi_i8:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fptosi<8 x half> %a to <8 x i8>
ret <8 x i8> %1
}
define <8 x i16> @fptosi_i16(<8 x half> %a) #0 {
-; CHECK-LABEL: fptosi_i16:
-; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
; CHECK-CVT_DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
; CHECK-CVT_DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
; CHECK-CVT_DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]]
@@ -419,194 +573,1057 @@ define <8 x i16> @fptosi_i16(<8 x half> %a) #0 {
; CHECK-CVT_DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]]
; CHECK-CVT_DAG: xtn2 [[I16]].8h, [[HIF32]]
; CHECK-COMMON_NEXT: ret
+; CHECK-CVT-LABEL: fptosi_i16:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtl2 v2.4s, v0.8h
+; CHECK-CVT-NEXT: fcvtzs v0.4s, v1.4s
+; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: fcvtzs v1.4s, v2.4s
+; CHECK-CVT-NEXT: xtn2 v0.8h, v1.4s
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-FP16-LABEL: fptosi_i16:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fptosi<8 x half> %a to <8 x i16>
ret <8 x i16> %1
}
define <8 x i8> @fptoui_i8(<8 x half> %a) #0 {
-; CHECK-LABEL: fptoui_i8:
-; CHECK-FP16-NEXT: fcvtzu [[LO:v[0-9]+\.8h]], v0.8h
-; CHECK-CVT-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
-; CHECK-CVT-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
-; CHECK-CVT-DAG: fcvtzu [[LOF32:v[0-9]+\.4s]], [[LO]]
-; CHECK-CVT-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]]
-; CHECK-CVT-DAG: fcvtzu [[HIF32:v[0-9]+\.4s]], [[HI]]
-; CHECK-CVT-DAG: xtn2 [[I16]].8h, [[HIF32]]
-; CHECK-CVT-DAG: xtn v0.8b, [[I16]].8h
-; CHECK-FP16-NEXT: xtn v0.8b, [[LO]]
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: fptoui_i8:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-CVT-NEXT: xtn v1.4h, v1.4s
+; CHECK-CVT-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-NEXT: xtn2 v1.8h, v0.4s
+; CHECK-CVT-NEXT: xtn v0.8b, v1.8h
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-FP16-LABEL: fptoui_i8:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fptoui<8 x half> %a to <8 x i8>
ret <8 x i8> %1
}
define <8 x i16> @fptoui_i16(<8 x half> %a) #0 {
-; CHECK-LABEL: fptoui_i16:
-; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-CVT-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
-; CHECK-CVT-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
-; CHECK-CVT-DAG: fcvtzu [[LOF32:v[0-9]+\.4s]], [[LO]]
-; CHECK-CVT-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]]
-; CHECK-CVT-DAG: fcvtzu [[HIF32:v[0-9]+\.4s]], [[HI]]
-; CHECK-CVT-DAG: xtn2 [[I16]].8h, [[HIF32]]
-; CHECK-NEXT: ret
+; CHECK-CVT-LABEL: fptoui_i16:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-NEXT: fcvtl2 v2.4s, v0.8h
+; CHECK-CVT-NEXT: fcvtzu v0.4s, v1.4s
+; CHECK-CVT-NEXT: xtn v0.4h, v0.4s
+; CHECK-CVT-NEXT: fcvtzu v1.4s, v2.4s
+; CHECK-CVT-NEXT: xtn2 v0.8h, v1.4s
+; CHECK-CVT-NEXT: ret
+;
+; CHECK-FP16-LABEL: fptoui_i16:
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fptoui<8 x half> %a to <8 x i16>
ret <8 x i16> %1
}
define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_une:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, ne
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, ne
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, ne
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, ne
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, ne
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, ne
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, ne
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, ne
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_une:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmeq v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp une <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_ueq:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: csetm w8, eq
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: csetm w9, eq
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csinv w9, w9, wzr, vc
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, eq
+; CHECK-CVT-NEXT: csinv w9, w9, wzr, vc
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, eq
+; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, eq
+; CHECK-CVT-NEXT: csinv w9, w9, wzr, vc
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: csetm w8, eq
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: csetm w8, eq
+; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[6], w8
+; CHECK-CVT-NEXT: csetm w8, eq
+; CHECK-CVT-NEXT: csinv w8, w8, wzr, vc
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_ueq:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
-; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmgt v2.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
+; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b
+; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp ueq <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_ugt:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, hi
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, hi
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, hi
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, hi
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, hi
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, hi
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, hi
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, hi
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_ugt:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmge v0.8h, v1.8h, v0.8h
+; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp ugt <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_uge:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, pl
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, pl
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, pl
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, pl
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, pl
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, pl
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, pl
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, pl
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_uge:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
+; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp uge <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_ult:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, lt
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, lt
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, lt
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, lt
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, lt
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, lt
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, lt
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, lt
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_ult:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmge v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp ult <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_ule:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, le
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, le
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, le
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, le
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, le
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, le
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, le
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, le
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_ule:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmgt v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp ule <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_uno:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, vs
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, vs
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, vs
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, vs
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, vs
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, vs
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, vs
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, vs
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_uno:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
-; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmge v2.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
+; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b
+; CHECK-FP16-NEXT: mvn v0.16b, v0.16b
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp uno <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_one:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: csetm w8, mi
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csinv w8, w8, wzr, le
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: csetm w9, mi
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csinv w9, w9, wzr, le
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, mi
+; CHECK-CVT-NEXT: csinv w9, w9, wzr, le
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, mi
+; CHECK-CVT-NEXT: csinv w8, w8, wzr, le
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, mi
+; CHECK-CVT-NEXT: csinv w9, w9, wzr, le
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: csetm w8, mi
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csinv w8, w8, wzr, le
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: csetm w8, mi
+; CHECK-CVT-NEXT: csinv w8, w8, wzr, le
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[6], w8
+; CHECK-CVT-NEXT: csetm w8, mi
+; CHECK-CVT-NEXT: csinv w8, w8, wzr, le
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_one:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
-; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmgt v2.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
+; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp one <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_oeq:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, eq
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, eq
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, eq
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, eq
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, eq
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, eq
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, eq
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, eq
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_oeq:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmeq v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp oeq <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_ogt:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, gt
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, gt
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, gt
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, gt
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, gt
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, gt
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, gt
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, gt
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_ogt:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmgt v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp ogt <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_oge:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, ge
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, ge
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, ge
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, ge
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, ge
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, ge
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, ge
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, ge
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_oge:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmge v0.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp oge <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_olt:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, mi
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, mi
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, mi
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, mi
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, mi
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, mi
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, mi
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, mi
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_olt:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp olt <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_ole:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, ls
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, ls
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, ls
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, ls
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, ls
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, ls
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, ls
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, ls
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_ole:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmge v0.8h, v1.8h, v0.8h
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp ole <8 x half> %a, %b
ret <8 x i1> %1
}
define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 {
-; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
-
+; CHECK-CVT-LABEL: test_fcmp_ord:
+; CHECK-CVT: // %bb.0:
+; CHECK-CVT-NEXT: mov h2, v1.h[1]
+; CHECK-CVT-NEXT: mov h3, v0.h[1]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s4, h1
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: fcvt s2, h0
+; CHECK-CVT-NEXT: mov h3, v1.h[2]
+; CHECK-CVT-NEXT: csetm w8, vc
+; CHECK-CVT-NEXT: fcmp s2, s4
+; CHECK-CVT-NEXT: mov h2, v0.h[2]
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: mov h4, v1.h[3]
+; CHECK-CVT-NEXT: csetm w9, vc
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v0.h[3]
+; CHECK-CVT-NEXT: fcvt s3, h4
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fmov s4, w9
+; CHECK-CVT-NEXT: csetm w9, vc
+; CHECK-CVT-NEXT: fcmp s2, s3
+; CHECK-CVT-NEXT: mov h2, v1.h[4]
+; CHECK-CVT-NEXT: mov h3, v0.h[4]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[1], w8
+; CHECK-CVT-NEXT: csetm w8, vc
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[5]
+; CHECK-CVT-NEXT: mov h3, v0.h[5]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[2], w9
+; CHECK-CVT-NEXT: csetm w9, vc
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov h2, v1.h[6]
+; CHECK-CVT-NEXT: mov h3, v0.h[6]
+; CHECK-CVT-NEXT: mov h1, v1.h[7]
+; CHECK-CVT-NEXT: mov h0, v0.h[7]
+; CHECK-CVT-NEXT: fcvt s2, h2
+; CHECK-CVT-NEXT: fcvt s3, h3
+; CHECK-CVT-NEXT: mov v4.h[3], w8
+; CHECK-CVT-NEXT: fcvt s1, h1
+; CHECK-CVT-NEXT: fcvt s0, h0
+; CHECK-CVT-NEXT: csetm w8, vc
+; CHECK-CVT-NEXT: fcmp s3, s2
+; CHECK-CVT-NEXT: mov v4.h[4], w9
+; CHECK-CVT-NEXT: csetm w9, vc
+; CHECK-CVT-NEXT: fcmp s0, s1
+; CHECK-CVT-NEXT: mov v4.h[5], w8
+; CHECK-CVT-NEXT: mov v4.h[6], w9
+; CHECK-CVT-NEXT: csetm w8, vc
+; CHECK-CVT-NEXT: mov v4.h[7], w8
+; CHECK-CVT-NEXT: xtn v0.8b, v4.8h
+; CHECK-CVT-NEXT: ret
+;
; CHECK-FP16-LABEL: test_fcmp_ord:
-; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
-; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
-
+; CHECK-FP16: // %bb.0:
+; CHECK-FP16-NEXT: fcmge v2.8h, v0.8h, v1.8h
+; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h
+; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b
+; CHECK-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-FP16-NEXT: ret
%1 = fcmp ord <8 x half> %a, %b
ret <8 x i1> %1
}
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