[PATCH] D107068: [DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D107068#2920603 <https://reviews.llvm.org/D107068#2920603>, @efriedma wrote:

> In D107068#2918827 <https://reviews.llvm.org/D107068#2918827>, @RKSimon wrote:
>
>> In D107068#2918791 <https://reviews.llvm.org/D107068#2918791>, @efriedma wrote:
>>
>>> Vector element mov is generally the same cost as zip1 on aarch64; zip1 is preferable because we can specify the destination register.
>>>
>>> https://github.com/llvm/llvm-project/blob/56e7b6c3924d7ba8db70c38235a77ed8208795eb/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L10552 is supposed to ensure that only INSERT_SUBVECTOR with index 0 is legal, I think?  Maybe it broke somehow.
>>
>> That only seems to be setup for scalable vectors - would it be better if I added a aarch64 combine that folds these to a CONCAT_VECTORS pattern?
>
> Oh, right.
>
> I guess saying NEON INSERT_SUBVECTOR is legal is fine.  We definitely do want to optimize to CONCAT_VECTORS where applicable, though.

OK, I'll drop the isel patterns and add a aarch64 combine to CONCAT_VECTORS instead.


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