[llvm] 7ed0120 - [AArch64][AsmParser] NFC: Parser.Lex() -> Lex()
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 2 02:49:01 PDT 2021
Author: Cullen Rhodes
Date: 2021-08-02T09:48:41Z
New Revision: 7ed0120d84d2e143bce1b9bd5f426f0bc8d53102
URL: https://github.com/llvm/llvm-project/commit/7ed0120d84d2e143bce1b9bd5f426f0bc8d53102
DIFF: https://github.com/llvm/llvm-project/commit/7ed0120d84d2e143bce1b9bd5f426f0bc8d53102.diff
LOG: [AArch64][AsmParser] NFC: Parser.Lex() -> Lex()
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D107146
Added:
Modified:
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 5866b65f0cc77..de68cc572b39b 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2672,7 +2672,6 @@ unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
/// the register is added to the operand list.
OperandMatchResultTy
AArch64AsmParser::tryParseScalarRegister(unsigned &RegNum) {
- MCAsmParser &Parser = getParser();
const AsmToken &Tok = getTok();
if (Tok.isNot(AsmToken::Identifier))
return MatchOperand_NoMatch;
@@ -2683,14 +2682,13 @@ AArch64AsmParser::tryParseScalarRegister(unsigned &RegNum) {
return MatchOperand_NoMatch;
RegNum = Reg;
- Parser.Lex(); // Eat identifier token.
+ Lex(); // Eat identifier token.
return MatchOperand_Success;
}
/// tryParseSysCROperand - Try to parse a system instruction CR operand name.
OperandMatchResultTy
AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
SMLoc S = getLoc();
if (getTok().isNot(AsmToken::Identifier)) {
@@ -2711,7 +2709,7 @@ AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
return MatchOperand_ParseFail;
}
- Parser.Lex(); // Eat identifier token.
+ Lex(); // Eat identifier token.
Operands.push_back(
AArch64Operand::CreateSysCR(CRNum, S, getLoc(), getContext()));
return MatchOperand_Success;
@@ -2721,7 +2719,6 @@ AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
template <bool IsSVEPrefetch>
OperandMatchResultTy
AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
SMLoc S = getLoc();
const AsmToken &Tok = getTok();
@@ -2783,14 +2780,13 @@ AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
Operands.push_back(AArch64Operand::CreatePrefetch(
*PRFM, Tok.getString(), S, getContext()));
- Parser.Lex(); // Eat identifier token.
+ Lex(); // Eat identifier token.
return MatchOperand_Success;
}
/// tryParsePSBHint - Try to parse a PSB operand, mapped to Hint command
OperandMatchResultTy
AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
SMLoc S = getLoc();
const AsmToken &Tok = getTok();
if (Tok.isNot(AsmToken::Identifier)) {
@@ -2806,14 +2802,13 @@ AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {
Operands.push_back(AArch64Operand::CreatePSBHint(
PSB->Encoding, Tok.getString(), S, getContext()));
- Parser.Lex(); // Eat identifier token.
+ Lex(); // Eat identifier token.
return MatchOperand_Success;
}
/// tryParseBTIHint - Try to parse a BTI operand, mapped to Hint command
OperandMatchResultTy
AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
SMLoc S = getLoc();
const AsmToken &Tok = getTok();
if (Tok.isNot(AsmToken::Identifier)) {
@@ -2829,7 +2824,7 @@ AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
Operands.push_back(AArch64Operand::CreateBTIHint(
BTI->Encoding, Tok.getString(), S, getContext()));
- Parser.Lex(); // Eat identifier token.
+ Lex(); // Eat identifier token.
return MatchOperand_Success;
}
@@ -2837,12 +2832,11 @@ AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
/// instruction.
OperandMatchResultTy
AArch64AsmParser::tryParseAdrpLabel(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
SMLoc S = getLoc();
const MCExpr *Expr = nullptr;
if (getTok().is(AsmToken::Hash)) {
- Parser.Lex(); // Eat hash token.
+ Lex(); // Eat hash token.
}
if (parseSymbolicImmVal(Expr))
@@ -2898,7 +2892,7 @@ AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
return MatchOperand_NoMatch;
if (getTok().is(AsmToken::Hash))
- getParser().Lex(); // Eat hash token.
+ Lex(); // Eat hash token.
if (parseSymbolicImmVal(Expr))
return MatchOperand_ParseFail;
@@ -2927,7 +2921,6 @@ AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
template<bool AddFPZeroAsLiteral>
OperandMatchResultTy
AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
SMLoc S = getLoc();
bool Hash = parseOptionalToken(AsmToken::Hash);
@@ -2974,7 +2967,7 @@ AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
RealVal, *StatusOrErr == APFloat::opOK, S, getContext()));
}
- Parser.Lex(); // Eat the token.
+ Lex(); // Eat the token.
return MatchOperand_Success;
}
@@ -2983,11 +2976,10 @@ AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
/// a shift suffix, for example '#1, lsl #12'.
OperandMatchResultTy
AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
SMLoc S = getLoc();
if (getTok().is(AsmToken::Hash))
- Parser.Lex(); // Eat '#'
+ Lex(); // Eat '#'
else if (getTok().isNot(AsmToken::Integer))
// Operand should start from # or should be integer, emit error otherwise.
return MatchOperand_NoMatch;
@@ -3002,7 +2994,7 @@ AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
}
// Eat ','
- Parser.Lex();
+ Lex();
// The optional operand must be "lsl #N" where N is non-negative.
if (!getTok().is(AsmToken::Identifier) ||
@@ -3012,7 +3004,7 @@ AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
}
// Eat 'lsl'
- Parser.Lex();
+ Lex();
parseOptionalToken(AsmToken::Hash);
@@ -3027,7 +3019,7 @@ AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
Error(getLoc(), "positive shift amount required");
return MatchOperand_ParseFail;
}
- Parser.Lex(); // Eat the number
+ Lex(); // Eat the number
// Just in case the optional lsl #0 is used for immediates other than zero.
if (ShiftAmount == 0 && Imm != nullptr) {
@@ -3085,7 +3077,6 @@ AArch64CC::CondCode AArch64AsmParser::parseCondCodeString(StringRef Cond) {
/// parseCondCode - Parse a Condition Code operand.
bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
bool invertCondCode) {
- MCAsmParser &Parser = getParser();
SMLoc S = getLoc();
const AsmToken &Tok = getTok();
assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
@@ -3094,7 +3085,7 @@ bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
AArch64CC::CondCode CC = parseCondCodeString(Cond);
if (CC == AArch64CC::Invalid)
return TokError("invalid condition code");
- Parser.Lex(); // Eat identifier token.
+ Lex(); // Eat identifier token.
if (invertCondCode) {
if (CC == AArch64CC::AL || CC == AArch64CC::NV)
@@ -3109,7 +3100,6 @@ bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
OperandMatchResultTy
AArch64AsmParser::tryParseSVCR(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
const AsmToken &Tok = getTok();
SMLoc S = getLoc();
@@ -3125,20 +3115,19 @@ AArch64AsmParser::tryParseSVCR(OperandVector &Operands) {
Operands.push_back(
AArch64Operand::CreateSVCR(PStateImm, Tok.getString(), S, getContext()));
- Parser.Lex(); // Eat identifier token.
+ Lex(); // Eat identifier token.
return MatchOperand_Success;
}
OperandMatchResultTy
AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
const AsmToken &Tok = getTok();
SMLoc S = getLoc();
StringRef Name = Tok.getString();
if (Name.equals_insensitive("za")) {
- Parser.Lex(); // eat "za"
+ Lex(); // eat "za"
Operands.push_back(AArch64Operand::CreateMatrixRegister(
AArch64::ZA, /*ElementWidth=*/0, MatrixKind::Array, S, getLoc(),
getContext()));
@@ -3176,7 +3165,7 @@ AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
}
unsigned ElementWidth = KindRes->second;
- Parser.Lex();
+ Lex();
Operands.push_back(AArch64Operand::CreateMatrixRegister(
Reg, ElementWidth, Kind, S, getLoc(), getContext()));
@@ -3194,7 +3183,6 @@ AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
/// them if present.
OperandMatchResultTy
AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
const AsmToken &Tok = getTok();
std::string LowerID = Tok.getString().lower();
AArch64_AM::ShiftExtendType ShOp =
@@ -3218,7 +3206,7 @@ AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
return MatchOperand_NoMatch;
SMLoc S = Tok.getLoc();
- Parser.Lex();
+ Lex();
bool Hash = parseOptionalToken(AsmToken::Hash);
@@ -3363,7 +3351,6 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
Mnemonic = Name;
Operands.push_back(AArch64Operand::CreateToken("sys", NameLoc, getContext()));
- MCAsmParser &Parser = getParser();
const AsmToken &Tok = getTok();
StringRef Op = Tok.getString();
SMLoc S = Tok.getLoc();
@@ -3427,7 +3414,7 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
createSysAlias(PRCTX->Encoding << 3 | PRCTX_Op2 , Operands, S);
}
- Parser.Lex(); // Eat operand.
+ Lex(); // Eat operand.
bool ExpectRegister = (Op.lower().find("all") == StringRef::npos);
bool HasRegister = false;
@@ -3518,14 +3505,13 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
Operands.push_back(AArch64Operand::CreateBarrier(
DB ? DB->Encoding : TSB->Encoding, Tok.getString(), getLoc(),
getContext(), false /*hasnXSModifier*/));
- Parser.Lex(); // Consume the option
+ Lex(); // Consume the option
return MatchOperand_Success;
}
OperandMatchResultTy
AArch64AsmParser::tryParseBarriernXSOperand(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
const AsmToken &Tok = getTok();
assert(Mnemonic == "dsb" && "Instruction does not accept nXS operands");
@@ -3573,14 +3559,13 @@ AArch64AsmParser::tryParseBarriernXSOperand(OperandVector &Operands) {
Operands.push_back(
AArch64Operand::CreateBarrier(DB->Encoding, Tok.getString(), getLoc(),
getContext(), true /*hasnXSModifier*/));
- Parser.Lex(); // Consume the option
+ Lex(); // Consume the option
return MatchOperand_Success;
}
OperandMatchResultTy
AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
const AsmToken &Tok = getTok();
if (Tok.isNot(AsmToken::Identifier))
@@ -3605,7 +3590,7 @@ AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
Operands.push_back(
AArch64Operand::CreateSysReg(Tok.getString(), getLoc(), MRSReg, MSRReg,
PStateImm, getContext()));
- Parser.Lex(); // Eat identifier
+ Lex(); // Eat identifier
return MatchOperand_Success;
}
@@ -3673,7 +3658,6 @@ AArch64AsmParser::tryParseVectorIndex(OperandVector &Operands) {
OperandMatchResultTy
AArch64AsmParser::tryParseVectorRegister(unsigned &Reg, StringRef &Kind,
RegKind MatchKind) {
- MCAsmParser &Parser = getParser();
const AsmToken &Tok = getTok();
if (Tok.isNot(AsmToken::Identifier))
@@ -3694,7 +3678,7 @@ AArch64AsmParser::tryParseVectorRegister(unsigned &Reg, StringRef &Kind,
return MatchOperand_ParseFail;
}
}
- Parser.Lex(); // Eat the register token.
+ Lex(); // Eat the register token.
Reg = RegNum;
return MatchOperand_Success;
@@ -3731,7 +3715,6 @@ AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
}
// Not all predicates are followed by a '/m' or '/z'.
- MCAsmParser &Parser = getParser();
if (getTok().isNot(AsmToken::Slash))
return MatchOperand_Success;
@@ -3744,7 +3727,7 @@ AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
// Add a literal slash as operand
Operands.push_back(AArch64Operand::CreateToken("/", getLoc(), getContext()));
- Parser.Lex(); // Eat the slash.
+ Lex(); // Eat the slash.
// Zeroing or merging?
auto Pred = getTok().getString().lower();
@@ -3757,7 +3740,7 @@ AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
const char *ZM = Pred == "z" ? "z" : "m";
Operands.push_back(AArch64Operand::CreateToken(ZM, getLoc(), getContext()));
- Parser.Lex(); // Eat zero/merge token.
+ Lex(); // Eat zero/merge token.
return MatchOperand_Success;
}
@@ -3775,7 +3758,6 @@ bool AArch64AsmParser::parseRegister(OperandVector &Operands) {
}
bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
- MCAsmParser &Parser = getParser();
bool HasELFModifier = false;
AArch64MCExpr::VariantKind RefKind;
@@ -3838,7 +3820,7 @@ bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
if (RefKind == AArch64MCExpr::VK_INVALID)
return TokError("expect relocation specifier in operand after ':'");
- Parser.Lex(); // Eat identifier
+ Lex(); // Eat identifier
if (parseToken(AsmToken::Colon, "expect ':' after relocation specifier"))
return true;
@@ -3999,7 +3981,7 @@ AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
SMLoc S = getLoc();
auto LCurly = getTok();
- Parser.Lex(); // Eat left bracket token.
+ Lex(); // Eat left bracket token.
StringRef Kind;
unsigned FirstReg;
@@ -4150,7 +4132,7 @@ AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
}
// Eat the comma
- getParser().Lex();
+ Lex();
// Match the shift
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> ExtOpnd;
@@ -4182,17 +4164,17 @@ bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
Operands.push_back(
AArch64Operand::CreateToken("mul", getLoc(), getContext()));
- Parser.Lex(); // Eat the "mul"
+ Lex(); // Eat the "mul"
if (NextIsVL) {
Operands.push_back(
AArch64Operand::CreateToken("vl", getLoc(), getContext()));
- Parser.Lex(); // Eat the "vl"
+ Lex(); // Eat the "vl"
return false;
}
if (NextIsHash) {
- Parser.Lex(); // Eat the #
+ Lex(); // Eat the #
SMLoc S = getLoc();
// Parse immediate operand.
@@ -4210,7 +4192,6 @@ bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
}
bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
- MCAsmParser &Parser = getParser();
auto Tok = getTok();
if (Tok.isNot(AsmToken::Identifier))
return true;
@@ -4223,7 +4204,7 @@ bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
Operands.push_back(
AArch64Operand::CreateToken(Keyword, Tok.getLoc(), getContext()));
- Parser.Lex();
+ Lex();
return false;
}
@@ -4262,7 +4243,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
case AsmToken::LBrac: {
Operands.push_back(
AArch64Operand::CreateToken("[", getLoc(), getContext()));
- Parser.Lex(); // Eat '['
+ Lex(); // Eat '['
// There's no comma after a '[', so we can parse the next operand
// immediately.
@@ -4274,7 +4255,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
Operands.push_back(
AArch64Operand::CreateToken("{", getLoc(), getContext()));
- Parser.Lex(); // Eat '{'
+ Lex(); // Eat '{'
// There's no comma after a '{', so we can parse the next operand
// immediately.
@@ -4335,7 +4316,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
// We need to consume this token only when we have a Real, otherwise
// we let parseSymbolicImmVal take care of it
if (Parser.getLexer().peekTok().is(AsmToken::Real))
- Parser.Lex();
+ Lex();
}
// The only Real that should come through here is a literal #0.0 for
@@ -4351,7 +4332,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
return TokError("unexpected floating point literal");
else if (IntVal != 0 || isNegative)
return TokError("expected floating-point constant #0.0");
- Parser.Lex(); // Eat the token.
+ Lex(); // Eat the token.
Operands.push_back(AArch64Operand::CreateToken("#0", S, getContext()));
Operands.push_back(AArch64Operand::CreateToken(".0", S, getContext()));
@@ -4370,7 +4351,7 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
SMLoc Loc = getLoc();
if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
return TokError("unexpected token in operand");
- Parser.Lex(); // Eat '='
+ Lex(); // Eat '='
const MCExpr *SubExprVal;
if (getParser().parseExpression(SubExprVal))
return true;
@@ -4432,7 +4413,7 @@ bool AArch64AsmParser::parseComma() {
if (check(getTok().isNot(AsmToken::Comma), getLoc(), "expected comma"))
return true;
// Eat the comma
- getParser().Lex();
+ Lex();
return false;
}
@@ -6261,8 +6242,7 @@ bool AArch64AsmParser::parseDirectiveLtorg(SMLoc L) {
/// parseDirectiveReq
/// ::= name .req registername
bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
- MCAsmParser &Parser = getParser();
- Parser.Lex(); // Eat the '.req' token.
+ Lex(); // Eat the '.req' token.
SMLoc SRegLoc = getLoc();
RegKind RegisterKind = RegKind::Scalar;
unsigned RegNum;
@@ -6325,11 +6305,10 @@ bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
/// parseDirectiveUneq
/// ::= .unreq registername
bool AArch64AsmParser::parseDirectiveUnreq(SMLoc L) {
- MCAsmParser &Parser = getParser();
if (getTok().isNot(AsmToken::Identifier))
return TokError("unexpected input in .unreq directive.");
RegisterReqs.erase(getTok().getIdentifier().lower());
- Parser.Lex(); // Eat the identifier.
+ Lex(); // Eat the identifier.
return parseToken(AsmToken::EndOfStatement);
}
@@ -6353,8 +6332,6 @@ bool AArch64AsmParser::parseDirectiveCFIBKeyFrame() {
/// parseDirectiveVariantPCS
/// ::= .variant_pcs symbolname
bool AArch64AsmParser::parseDirectiveVariantPCS(SMLoc L) {
- MCAsmParser &Parser = getParser();
-
const AsmToken &Tok = getTok();
if (Tok.isNot(AsmToken::Identifier))
return TokError("expected symbol name");
@@ -6365,7 +6342,7 @@ bool AArch64AsmParser::parseDirectiveVariantPCS(SMLoc L) {
if (!Sym)
return TokError("unknown symbol");
- Parser.Lex(); // Eat the symbol
+ Lex(); // Eat the symbol
if (parseEOL())
return true;
@@ -6774,7 +6751,7 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
return MatchOperand_ParseFail;
}
// Eat the comma
- getParser().Lex();
+ Lex();
SMLoc E = getLoc();
unsigned SecondReg;
@@ -6840,7 +6817,7 @@ AArch64AsmParser::tryParseSVEDataVector(OperandVector &Operands) {
}
// Eat the comma
- getParser().Lex();
+ Lex();
// Match the shift
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> ExtOpnd;
@@ -6870,7 +6847,7 @@ AArch64AsmParser::tryParseSVEPattern(OperandVector &Operands) {
int64_t Pattern;
if (IsHash) {
- Parser.Lex(); // Eat hash
+ Lex(); // Eat hash
// Parse the immediate operand.
const MCExpr *ImmVal;
@@ -6889,7 +6866,7 @@ AArch64AsmParser::tryParseSVEPattern(OperandVector &Operands) {
if (!Pat)
return MatchOperand_NoMatch;
- Parser.Lex();
+ Lex();
Pattern = Pat->Encoding;
assert(Pattern >= 0 && Pattern < 32);
}
More information about the llvm-commits
mailing list