[llvm] d268c20 - [X86] Support auto-detect for tigerlake and alderlake

[Freddy Ye via llvm-commits]

Author: Freddy Ye
Date: 2021-08-02T11:01:01+08:00
New Revision: d268c200701777085ef5d19e4a0637b87c7a02ac

URL: https://github.com/llvm/llvm-project/commit/d268c200701777085ef5d19e4a0637b87c7a02ac
DIFF: https://github.com/llvm/llvm-project/commit/d268c200701777085ef5d19e4a0637b87c7a02ac.diff

LOG: [X86] Support auto-detect for tigerlake and alderlake

Differential Revision: https://reviews.llvm.org/D107245

Added: 
    

Modified: 
    compiler-rt/lib/builtins/cpu_model.c
    llvm/lib/Support/Host.cpp

Removed: 
    


################################################################################
diff  --git a/compiler-rt/lib/builtins/cpu_model.c b/compiler-rt/lib/builtins/cpu_model.c
index 6ee42911b204a..b8d807ed651c9 100644
--- a/compiler-rt/lib/builtins/cpu_model.c
+++ b/compiler-rt/lib/builtins/cpu_model.c
@@ -422,6 +422,22 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
       *Subtype = INTEL_COREI7_ICELAKE_CLIENT;
       break;
 
+    // Tigerlake:
+    case 0x8c:
+    case 0x8d:
+      CPU = "tigerlake";
+      *Type = INTEL_COREI7;
+      *Subtype = INTEL_COREI7_TIGERLAKE;
+      break;
+
+    // Alderlake:
+    case 0x97:
+    case 0x9a:
+      CPU = "alderlake";
+      *Type = INTEL_COREI7;
+      *Subtype = INTEL_COREI7_ALDERLAKE;
+      break;
+
     // Icelake Xeon:
     case 0x6a:
     case 0x6c:

diff  --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp
index f873ff06f1f73..5137c277e6ebf 100644
--- a/llvm/lib/Support/Host.cpp
+++ b/llvm/lib/Support/Host.cpp
@@ -772,6 +772,22 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
       *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
       break;
 
+    // Tigerlake:
+    case 0x8c:
+    case 0x8d:
+      CPU = "tigerlake";
+      *Type = X86::INTEL_COREI7;
+      *Subtype = X86::INTEL_COREI7_TIGERLAKE;
+      break;
+
+    // Alderlake:
+    case 0x97:
+    case 0x9a:
+      CPU = "alderlake";
+      *Type = X86::INTEL_COREI7;
+      *Subtype = X86::INTEL_COREI7_ALDERLAKE;
+      break;
+
     // Icelake Xeon:
     case 0x6a:
     case 0x6c: