[llvm] ee3aef9 - [RISCV][Docs] Add description about inline asm constraint for V.

[Hsiangkai Wang via llvm-commits]

Author: Hsiangkai Wang
Date: 2021-08-01T05:58:17+08:00
New Revision: ee3aef93b73646ef98f0241498d807a4fb68b78c

URL: https://github.com/llvm/llvm-project/commit/ee3aef93b73646ef98f0241498d807a4fb68b78c
DIFF: https://github.com/llvm/llvm-project/commit/ee3aef93b73646ef98f0241498d807a4fb68b78c.diff

LOG: [RISCV][Docs] Add description about inline asm constraint for V.

Add inline asm constraint 'vr' for vector registers and 'vm' for vector
mask registers.

Differential Revision: https://reviews.llvm.org/D106633

Added: 
    

Modified: 
    llvm/docs/LangRef.rst

Removed: 
    


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diff  --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index d5e4e596475a..d91464a157ee 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -4779,6 +4779,8 @@ RISC-V:
 - ``f``: A 32- or 64-bit floating-point register (requires F or D extension).
 - ``r``: A 32- or 64-bit general-purpose register (depending on the platform
   ``XLEN``).
+- ``vr``: A vector register. (requires V extension).
+- ``vm``: A vector mask register. (requires V extension).
 
 Sparc: