[PATCH] D107210: [RISCV] Support interleaved load lowering

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Don't you need to add the InterleavedAccess pass to RISCVTargetMachine?



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:996
+  Type *Tys[2] = {FVTy, PtrTy};
+  static const Intrinsic::ID LoadInts[3] = {Intrinsic::riscv_vlseg2,
+                                            Intrinsic::riscv_vlseg3,
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These intrinsics only have SelectionDAG support for scalable vector types. And they take VL as an operand.


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https://reviews.llvm.org/D107210