[PATCH] D107196: [AArch64InstPrinter] Change printAddSubImm to only add imm value comment when shifted

Fri Jul 30 14:48:48 PDT 2021

jasonmolenda created this revision.
jasonmolenda added a reviewer: t.p.northover.
jasonmolenda added a project: LLVM.
Herald added subscribers: danielkiss, asbirlea, rupprecht, arphaman, hiraditya, kristof.beyls, arichardson, emaste.
Herald added a reviewer: jhenderson.
Herald added a reviewer: MaskRay.
jasonmolenda requested review of this revision.

AArch64InstPrinter::printAddSubImm adds an immediate value to the comment stream when both are available.  This is helpful when the imm value is shifted, e.g.

  add x9, x0, #291, lsl #12 ; =1191936

but most of the time it looks like

  subs x9, x0, #256 ; =256

where the comment adds nothing useful.

This patch changes printAddSubImm so it only appends the immediate value to the comment stream when it has a shift.  The majority of the patchset is updating the tests to match the new output style.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107196

Files:
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
  llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
  llvm/test/CodeGen/AArch64/GlobalISel/freeze.ll
  llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
  llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
  llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
  llvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll
  llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
  llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
  llvm/test/CodeGen/AArch64/addsub.ll
  llvm/test/CodeGen/AArch64/align-down.ll
  llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
  llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
  llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
  llvm/test/CodeGen/AArch64/arm64-ccmp.ll
  llvm/test/CodeGen/AArch64/arm64-fp128.ll
  llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
  llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
  llvm/test/CodeGen/AArch64/arm64-nvcast.ll
  llvm/test/CodeGen/AArch64/arm64-popcnt.ll
  llvm/test/CodeGen/AArch64/arm64-rev.ll
  llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
  llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
  llvm/test/CodeGen/AArch64/branch-relax-bcc.ll
  llvm/test/CodeGen/AArch64/branch-relax-cbz.ll
  llvm/test/CodeGen/AArch64/cgp-usubo.ll
  llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
  llvm/test/CodeGen/AArch64/cmp-select-sign.ll
  llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
  llvm/test/CodeGen/AArch64/extract-bits.ll
  llvm/test/CodeGen/AArch64/extract-lowbits.ll
  llvm/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll
  llvm/test/CodeGen/AArch64/fast-isel-sdiv.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/funnel-shift.ll
  llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
  llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
  llvm/test/CodeGen/AArch64/implicit-null-check.ll
  llvm/test/CodeGen/AArch64/inc-of-add.ll
  llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
  llvm/test/CodeGen/AArch64/lack-of-signed-truncation-check.ll
  llvm/test/CodeGen/AArch64/ldst-paired-aliasing.ll
  llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
  llvm/test/CodeGen/AArch64/machine-licm-sink-instr.ll
  llvm/test/CodeGen/AArch64/machine-outliner-thunk.ll
  llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
  llvm/test/CodeGen/AArch64/neg-abs.ll
  llvm/test/CodeGen/AArch64/pow.ll
  llvm/test/CodeGen/AArch64/pr48188.ll
  llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
  llvm/test/CodeGen/AArch64/sadd_sat.ll
  llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/sat-add.ll
  llvm/test/CodeGen/AArch64/sdivpow2.ll
  llvm/test/CodeGen/AArch64/select_const.ll
  llvm/test/CodeGen/AArch64/shift-mod.ll
  llvm/test/CodeGen/AArch64/signbit-shift.ll
  llvm/test/CodeGen/AArch64/signed-truncation-check.ll
  llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
  llvm/test/CodeGen/AArch64/split-vector-insert.ll
  llvm/test/CodeGen/AArch64/srem-lkk.ll
  llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/srem-seteq.ll
  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/ssub_sat.ll
  llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
  llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
  llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
  llvm/test/CodeGen/AArch64/sub-of-not.ll
  llvm/test/CodeGen/AArch64/sub1.ll
  llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
  llvm/test/CodeGen/AArch64/sve-extract-vector.ll
  llvm/test/CodeGen/AArch64/sve-insert-element.ll
  llvm/test/CodeGen/AArch64/sve-insert-vector.ll
  llvm/test/CodeGen/AArch64/sve-ld1r.ll
  llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
  llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
  llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
  llvm/test/CodeGen/AArch64/uadd_sat.ll
  llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
  llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/uaddo.ll
  llvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/AArch64/unwind-preserved.ll
  llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll
  llvm/test/CodeGen/AArch64/urem-seteq.ll
  llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
  llvm/test/CodeGen/AArch64/usub_sat_vec.ll
  llvm/test/CodeGen/AArch64/vec-libcalls.ll
  llvm/test/CodeGen/AArch64/vec_uaddo.ll
  llvm/test/CodeGen/AArch64/vec_umulo.ll
  llvm/test/CodeGen/AArch64/vecreduce-bool.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
  llvm/test/CodeGen/AArch64/vldn_shuffle.ll
  llvm/test/CodeGen/AArch64/wineh-try-catch-nobase.ll
  llvm/test/Transforms/CanonicalizeFreezeInLoops/aarch64.ll
  llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-pre-inc-offset-check.ll
  llvm/test/Transforms/LoopStrengthReduce/AArch64/small-constant.ll
  llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.generated.expected
  llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/aarch64_generated_funcs.ll.nogenerated.expected
  llvm/test/tools/llvm-objdump/ELF/AArch64/disassemble-align.s

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