[PATCH] D94096: [AArch64] Add a Machine Value Type for 8 consecutive registers
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 30 14:31:20 PDT 2021
efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.
LGTM.
It's a little unfortunate we need a dedicated valuetype just for usage in inline asm, but I don't see a good alternative; at least, not without substantially rewriting the inline asm handling.
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https://reviews.llvm.org/D94096/new/
https://reviews.llvm.org/D94096
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