[PATCH] D107187: [amdgpu] Add an enhanced conversion from i64 to f32.

[Michael Liao via Phabricator via llvm-commits]

hliao added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:2530
+    // Count the leading zeros.
+    ShAmt = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Hi);
+    ShAmt = DAG.getSelect(SL, MVT::i32,
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arsenm wrote:
> Why is zero undef OK? The high half could be all zeroes
For the all 0 case, the following 'select' will return 32, so that all hi bits are shifted out. In that case, only the low 32 bits need converting.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:2118-2119
+  auto Scale = B.buildSub(S32, B.buildConstant(S32, 32), ShAmt);
+  SmallVector<Register, 1> Results;
+  Results.push_back(Dst);
+  B.buildIntrinsic(Intrinsic::amdgcn_ldexp, Results, /*HasSideEffects=*/false)
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arsenm wrote:
> You can just do {Dst} directly to the buildInstr call
I remembered I tried that but still cannot compile it. Let me try again


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https://reviews.llvm.org/D107187