[PATCH] D106549: [AArch64][SVE] Combine bitcasts to predicate types with vector inserts of loads

[Bradley Smith via Phabricator via llvm-commits]

bsmith updated this revision to Diff 363041.
bsmith marked 8 inline comments as done.
bsmith added a comment.

- Avoid iterating over the instructions twice
- Rename function to better reflect what they are doing
- Disallow Vscale == 0 case
- Only allow optimization when the fixed type involved is of i8 type
- Relax only one use requirements
- Only remove instructions when there are no more uses


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106549/new/

https://reviews.llvm.org/D106549

Files:
  llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp
  llvm/test/CodeGen/AArch64/sve-extract-vector-to-predicate-store.ll
  llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll

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