[llvm] 754520a - [PowerPC] Fix issue where hint was providing the incorrect regsiter class.

[Stefan Pintilie via llvm-commits]

Author: Stefan Pintilie
Date: 2021-07-29T21:10:45-05:00
New Revision: 754520a2bf55a0873753efb1d863a5ffd116c48b

URL: https://github.com/llvm/llvm-project/commit/754520a2bf55a0873753efb1d863a5ffd116c48b
DIFF: https://github.com/llvm/llvm-project/commit/754520a2bf55a0873753efb1d863a5ffd116c48b.diff

LOG: [PowerPC] Fix issue where hint was providing the incorrect regsiter class.

Regsier hints when copying to a UACC register do not always produce VSRp
registers. This patch makes sure that we do not produce hints in cases
where the subregsiter of the UACC is not a VSRp.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D107101

Added: 
    llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll

Modified: 
    llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 4f16c7f5ff17..ca8ca80a7f57 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -506,7 +506,9 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
           VRM->hasPhys(ResultReg)) {
         Register UACCPhys = VRM->getPhys(ResultReg);
         Register HintReg = getSubReg(UACCPhys, ResultOp->getSubReg());
-        Hints.push_back(HintReg);
+        // Ensure that the hint is a VSRp register.
+        if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31)
+          Hints.push_back(HintReg);
       }
       break;
     }

diff  --git a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
new file mode 100644
index 000000000000..154be01d9cc9
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
+; RUN:    | FileCheck %s
+
+define void @copy_novsrp() local_unnamed_addr {
+; CHECK-LABEL: copy_novsrp:
+; CHECK:       # %bb.0: # %dmblvi_entry
+; CHECK-NEXT:    xxlxor v2, v2, v2
+; CHECK-NEXT:    xxlxor vs0, vs0, vs0
+; CHECK-NEXT:    xxlor vs3, v2, v2
+; CHECK-NEXT:    stxv vs1, 0(0)
+dmblvi_entry:
+  %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
+  %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
+  %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
+  store <16 x i8> %2, <16 x i8>* null, align 1
+  unreachable
+}
+
+declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
+declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)