[llvm] e622c99 - [ARC] Add norm/normh instructions with disassembly tests

[Mark Schimmel via llvm-commits]

Author: Mark Schimmel
Date: 2021-07-29T17:54:52-07:00
New Revision: e622c99f305dc1fe9385742079a9ac6f81f86d2e

URL: https://github.com/llvm/llvm-project/commit/e622c99f305dc1fe9385742079a9ac6f81f86d2e
DIFF: https://github.com/llvm/llvm-project/commit/e622c99f305dc1fe9385742079a9ac6f81f86d2e.diff

LOG: [ARC] Add norm/normh instructions with disassembly tests
Add disassembler support for the NORM and NORMH instructions. These instructions
only exist when the ARC processor is configured with the "norm" extension.

fferential Revision: https://reviews.llvm.org/D107118

Added: 
    

Modified: 
    llvm/lib/Target/ARC/ARCInstrInfo.td
    llvm/test/MC/Disassembler/ARC/misc.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARC/ARCInstrInfo.td b/llvm/lib/Target/ARC/ARCInstrInfo.td
index c016cd4bcf39..16c3e50635bf 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.td
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.td
@@ -45,7 +45,6 @@ def SDT_ARCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
 def SDT_ARCCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
                                          SDTCisVT<1, i32> ]>;
 
-
 // Global Address.
 def ARCGAWrapper : SDNode<"ARCISD::GAWRAPPER", SDT_ARCmov, []>;
 
@@ -79,6 +78,12 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARCCallSeqStart,
 def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_ARCCallSeqEnd,
                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
+//===----------------------------------------------------------------------===//
+// Instruction predicates
+//===----------------------------------------------------------------------===//
+
+def HasNorm  :       Predicate<"Subtarget->hasNorm()">;
+
 //===----------------------------------------------------------------------===//
 // Instruction Pattern Stuff
 //===----------------------------------------------------------------------===//
@@ -303,6 +308,11 @@ defm SEXH : ArcUnaryGEN4Inst<0b000110, "sexh">;
 // Extension unary instruction definitions.
 defm FLS : ArcUnaryEXT5Inst<0b010011, "fls">;
 
+let Predicates=[HasNorm] in {
+  defm NORM  : ArcUnaryEXT5Inst<0b000001,"norm">;
+  defm NORMH : ArcUnaryEXT5Inst<0b001000,"normh">;
+}
+
 // General Unary Instruction fragments.
 def : Pat<(sext_inreg i32:$a, i8), (SEXB_rr i32:$a)>;
 def : Pat<(sext_inreg i32:$a, i16), (SEXH_rr i32:$a)>;

diff  --git a/llvm/test/MC/Disassembler/ARC/misc.txt b/llvm/test/MC/Disassembler/ARC/misc.txt
index 2abe46a929e8..45ba9b00382d 100644
--- a/llvm/test/MC/Disassembler/ARC/misc.txt
+++ b/llvm/test/MC/Disassembler/ARC/misc.txt
@@ -129,3 +129,9 @@
 
 # CHECK: fls.f %r0, %r0
 0x2f 0x28 0x13 0x80
+
+# CHECK: norm %r22, %blink
+0x2f 0x2e 0xc1 0x27
+
+# CHECK: normh %r7, %r18
+0x2f 0x2f 0x88 0x04