[llvm] 811be79 - [RISCV][test] Add new tests for mul optimization in the zba extension with SH*ADD
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 29 17:36:52 PDT 2021
Author: Ben Shi
Date: 2021-07-30T08:36:28+08:00
New Revision: 811be79433638c3c7eeea65f5438044a5ba8de9a
URL: https://github.com/llvm/llvm-project/commit/811be79433638c3c7eeea65f5438044a5ba8de9a
DIFF: https://github.com/llvm/llvm-project/commit/811be79433638c3c7eeea65f5438044a5ba8de9a.diff
LOG: [RISCV][test] Add new tests for mul optimization in the zba extension with SH*ADD
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D107064
Added:
Modified:
llvm/test/CodeGen/RISCV/rv32zba.ll
llvm/test/CodeGen/RISCV/rv64zba.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv32zba.ll b/llvm/test/CodeGen/RISCV/rv32zba.ll
index 31eaed57d6d2..22d6f7444970 100644
--- a/llvm/test/CodeGen/RISCV/rv32zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zba.ll
@@ -605,6 +605,72 @@ define i32 @mul73(i32 %a) {
ret i32 %c
}
+define i32 @mul27(i32 %a) {
+; RV32I-LABEL: mul27:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 27
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul27:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 27
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul27:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 27
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 27
+ ret i32 %c
+}
+
+define i32 @mul45(i32 %a) {
+; RV32I-LABEL: mul45:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 45
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul45:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 45
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul45:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 45
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 45
+ ret i32 %c
+}
+
+define i32 @mul81(i32 %a) {
+; RV32I-LABEL: mul81:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 81
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul81:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 81
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul81:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 81
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 81
+ ret i32 %c
+}
+
define i32 @mul4098(i32 %a) {
; RV32I-LABEL: mul4098:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index b61b9192e4c5..f4707a8dfed1 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -1110,6 +1110,72 @@ define i64 @mul73(i64 %a) {
ret i64 %c
}
+define i64 @mul27(i64 %a) {
+; RV64I-LABEL: mul27:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 27
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul27:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 27
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul27:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 27
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 27
+ ret i64 %c
+}
+
+define i64 @mul45(i64 %a) {
+; RV64I-LABEL: mul45:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 45
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul45:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 45
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul45:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 45
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 45
+ ret i64 %c
+}
+
+define i64 @mul81(i64 %a) {
+; RV64I-LABEL: mul81:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 81
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul81:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 81
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul81:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 81
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 81
+ ret i64 %c
+}
+
define i64 @mul4098(i64 %a) {
; RV64I-LABEL: mul4098:
; RV64I: # %bb.0:
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