[PATCH] D107118: [ARC] Add norm/normh instructions with disassembly tests

[Mark Schimmel via Phabricator via llvm-commits]

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Add disassembler support for the NORM and NORMH instructions. These instructions only exist when the ARC processor is configured with the "norm" extension.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107118

Files:
  llvm/lib/Target/ARC/ARCInstrInfo.td
  llvm/test/MC/Disassembler/ARC/misc.txt


Index: llvm/test/MC/Disassembler/ARC/misc.txt
===================================================================
--- llvm/test/MC/Disassembler/ARC/misc.txt
+++ llvm/test/MC/Disassembler/ARC/misc.txt
@@ -66,3 +66,9 @@
 
 # CHECK: fls.f %r0, %r0
 0x2f 0x28 0x13 0x80
+
+# CHECK: norm %r22, %blink
+0x2f 0x2e 0xc1 0x27
+
+# CHECK: normh %r7, %r18
+0x2f 0x2f 0x88 0x04
Index: llvm/lib/Target/ARC/ARCInstrInfo.td
===================================================================
--- llvm/lib/Target/ARC/ARCInstrInfo.td
+++ llvm/lib/Target/ARC/ARCInstrInfo.td
@@ -79,6 +79,12 @@
 def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_ARCCallSeqEnd,
                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
+//===----------------------------------------------------------------------===//
+// Instruction predicates
+//===----------------------------------------------------------------------===//
+
+def HasNorm  :       Predicate<"Subtarget->hasNorm()">;
+
 //===----------------------------------------------------------------------===//
 // Instruction Pattern Stuff
 //===----------------------------------------------------------------------===//
@@ -303,6 +309,11 @@
 // Extension unary instruction definitions.
 defm FLS : ArcUnaryEXT5Inst<0b010011, "fls">;
 
+let Predicates=[HasNorm] in {
+  defm NORM  : ArcUnaryEXT5Inst<0b000001,"norm">;
+  defm NORMH : ArcUnaryEXT5Inst<0b001000,"normh">;
+}
+
 // General Unary Instruction fragments.
 def : Pat<(sext_inreg i32:$a, i8), (SEXB_rr i32:$a)>;
 def : Pat<(sext_inreg i32:$a, i16), (SEXH_rr i32:$a)>;


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