[PATCH] D107086: [Lanai] fix lowering wide returns

[Serge Bazanski via Phabricator via llvm-commits]

q3k updated this revision to Diff 362816.
q3k added a comment.

Ran clang-tidy.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107086/new/

https://reviews.llvm.org/D107086

Files:
  llvm/lib/Target/Lanai/LanaiISelLowering.cpp
  llvm/lib/Target/Lanai/LanaiISelLowering.h
  llvm/test/CodeGen/Lanai/lowering-128.ll


Index: llvm/test/CodeGen/Lanai/lowering-128.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Lanai/lowering-128.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=lanai < %s | FileCheck %s
+
+; Tests that lowering wide registers (128 bits or more) works on Lanai.
+; The emitted assembly is not checked, we just do a smoketest.
+
+target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
+target triple = "lanai"
+
+; CHECK-LABEL: add128:
+define i128 @add128(i128 %x, i128 %y) {
+  %a = add i128 %x, %y
+  ret i128 %a
+}
+
Index: llvm/lib/Target/Lanai/LanaiISelLowering.h
===================================================================
--- llvm/lib/Target/Lanai/LanaiISelLowering.h
+++ llvm/lib/Target/Lanai/LanaiISelLowering.h
@@ -90,6 +90,11 @@
   SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 
+  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+                      bool IsVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      LLVMContext &Context) const override;
+
   Register getRegisterByName(const char *RegName, LLT VT,
                              const MachineFunction &MF) const override;
   std::pair<unsigned, const TargetRegisterClass *>
Index: llvm/lib/Target/Lanai/LanaiISelLowering.cpp
===================================================================
--- llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -530,6 +530,15 @@
   return Chain;
 }
 
+bool LanaiTargetLowering::CanLowerReturn(
+    CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
+
+  return CCInfo.CheckReturn(Outs, RetCC_Lanai32);
+}
+
 SDValue
 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                                  bool IsVarArg,


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