[PATCH] D105130: [RISCV] Enable interleaved access vectorization

[Luke via Phabricator via llvm-commits]

luke957 added a comment.

In D105130#2909217 <https://reviews.llvm.org/D105130#2909217>, @craig.topper wrote:

> If we aren't using segment load/store, what does the backend codegen for this look like?

It looks like this

  %wide.vec = load <8 x i32>, <8 x i32>* %1, align 4
  %strided.vec = shufflevector <8 x i32> %wide.vec, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %strided.vec1 = shufflevector <8 x i32> %wide.vec, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  ...
  %interleaved.vec = shufflevector <4 x i32> %3, <4 x i32> %4, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
  store <8 x i32> %interleaved.vec, <8 x i32>* %7, align 4

InnerLoopVectorizer::vectorizeInterleaveGroup() will generate shufflevector instructions for interleaved accesses.


Repository:
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  https://reviews.llvm.org/D105130/new/

https://reviews.llvm.org/D105130