[llvm] 3d157fb - [NFC][Codegen][X86] Autogenerate check lines in avx.ll test
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 28 15:25:22 PDT 2021
Author: Roman Lebedev
Date: 2021-07-29T01:09:59+03:00
New Revision: 3d157fb627e0fdb1600c3051dcbd0c4c221083a6
URL: https://github.com/llvm/llvm-project/commit/3d157fb627e0fdb1600c3051dcbd0c4c221083a6
DIFF: https://github.com/llvm/llvm-project/commit/3d157fb627e0fdb1600c3051dcbd0c4c221083a6.diff
LOG: [NFC][Codegen][X86] Autogenerate check lines in avx.ll test
Added:
Modified:
llvm/test/CodeGen/X86/avx.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/avx.ll b/llvm/test/CodeGen/X86/avx.ll
index d0801f258834b..a176edba13aa9 100644
--- a/llvm/test/CodeGen/X86/avx.ll
+++ b/llvm/test/CodeGen/X86/avx.ll
@@ -1,26 +1,41 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx | FileCheck %s --check-prefixes=X32,CHECK
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx | FileCheck %s --check-prefixes=CHECK,X32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s --check-prefixes=CHECK,X64
define <4 x i32> @blendvb_fallback_v4i32(<4 x i1> %mask, <4 x i32> %x, <4 x i32> %y) {
-; CHECK-LABEL: @blendvb_fallback_v4i32
-; CHECK: vblendvps
-; CHECK: ret
+; CHECK-LABEL: blendvb_fallback_v4i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
+; CHECK-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
+; CHECK-NEXT: ret{{[l|q]}}
%ret = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %y
ret <4 x i32> %ret
}
define <8 x i32> @blendvb_fallback_v8i32(<8 x i1> %mask, <8 x i32> %x, <8 x i32> %y) {
-; CHECK-LABEL: @blendvb_fallback_v8i32
-; CHECK: vblendvps
-; CHECK: ret
+; CHECK-LABEL: blendvb_fallback_v8i32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; CHECK-NEXT: vpslld $31, %xmm3, %xmm3
+; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
+; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
+; CHECK-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
ret <8 x i32> %ret
}
define <8 x float> @blendvb_fallback_v8f32(<8 x i1> %mask, <8 x float> %x, <8 x float> %y) {
-; CHECK-LABEL: @blendvb_fallback_v8f32
-; CHECK: vblendvps
-; CHECK: ret
+; CHECK-LABEL: blendvb_fallback_v8f32:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; CHECK-NEXT: vpslld $31, %xmm3, %xmm3
+; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
+; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
+; CHECK-NEXT: vblendvps %ymm0, %ymm1, %ymm2, %ymm0
+; CHECK-NEXT: ret{{[l|q]}}
%ret = select <8 x i1> %mask, <8 x float> %x, <8 x float> %y
ret <8 x float> %ret
}
@@ -28,12 +43,17 @@ define <8 x float> @blendvb_fallback_v8f32(<8 x i1> %mask, <8 x float> %x, <8 x
declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
-; CHECK-LABEL: insertps_from_vector_load:
; On X32, account for the argument's move to registers
-; X32: movl 4(%esp), %eax
-; CHECK-NOT: mov
-; CHECK: vinsertps $48, (%{{...}}), {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
-; CHECK-NEXT: ret
+; X32-LABEL: insertps_from_vector_load:
+; X32: ## %bb.0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; X32-NEXT: retl
+;
+; X64-LABEL: insertps_from_vector_load:
+; X64: ## %bb.0:
+; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; X64-NEXT: retq
%1 = load <4 x float>, <4 x float>* %pb, align 16
%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 48)
ret <4 x float> %2
@@ -41,27 +61,39 @@ define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocap
;; Use a non-zero CountS for insertps
define <4 x float> @insertps_from_vector_load_offset(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
-; CHECK-LABEL: insertps_from_vector_load_offset:
; On X32, account for the argument's move to registers
-; X32: movl 4(%esp), %eax
-; CHECK-NOT: mov
;; Try to match a bit more of the instr, since we need the load's offset.
-; CHECK: vinsertps $32, 4(%{{...}}), {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
-; CHECK-NEXT: ret
+; X32-LABEL: insertps_from_vector_load_offset:
+; X32: ## %bb.0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
+; X32-NEXT: retl
+;
+; X64-LABEL: insertps_from_vector_load_offset:
+; X64: ## %bb.0:
+; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
+; X64-NEXT: retq
%1 = load <4 x float>, <4 x float>* %pb, align 16
%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
ret <4 x float> %2
}
define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x float>* nocapture readonly %pb, i64 %index) {
-; CHECK-LABEL: insertps_from_vector_load_offset_2:
; On X32, account for the argument's move to registers
-; X32: movl 4(%esp), %eax
-; X32: movl 8(%esp), %ecx
-; CHECK-NOT: mov
;; Try to match a bit more of the instr, since we need the load's offset.
-; CHECK: vinsertps $0, 12(%{{...}},%{{...}}), {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]
-; CHECK-NEXT: ret
+; X32-LABEL: insertps_from_vector_load_offset_2:
+; X32: ## %bb.0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT: shll $4, %ecx
+; X32-NEXT: vinsertps {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]
+; X32-NEXT: retl
+;
+; X64-LABEL: insertps_from_vector_load_offset_2:
+; X64: ## %bb.0:
+; X64-NEXT: shlq $4, %rsi
+; X64-NEXT: vinsertps {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]
+; X64-NEXT: retq
%1 = getelementptr inbounds <4 x float>, <4 x float>* %pb, i64 %index
%2 = load <4 x float>, <4 x float>* %1, align 16
%3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
@@ -69,13 +101,18 @@ define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x floa
}
define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocapture readonly %fb, i64 %index) {
-; CHECK-LABEL: insertps_from_broadcast_loadf32:
; On X32, account for the arguments' move to registers
-; X32: movl 8(%esp), %eax
-; X32: movl 4(%esp), %ecx
-; CHECK-NOT: mov
-; CHECK: insertps $48
-; CHECK-NEXT: ret
+; X32-LABEL: insertps_from_broadcast_loadf32:
+; X32: ## %bb.0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; X32-NEXT: retl
+;
+; X64-LABEL: insertps_from_broadcast_loadf32:
+; X64: ## %bb.0:
+; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; X64-NEXT: retq
%1 = getelementptr inbounds float, float* %fb, i64 %index
%2 = load float, float* %1, align 4
%3 = insertelement <4 x float> undef, float %2, i32 0
@@ -87,12 +124,17 @@ define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocap
}
define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float>* nocapture readonly %b) {
-; CHECK-LABEL: insertps_from_broadcast_loadv4f32:
; On X32, account for the arguments' move to registers
-; X32: movl 4(%esp), %{{...}}
-; CHECK-NOT: mov
-; CHECK: insertps $48
-; CHECK-NEXT: ret
+; X32-LABEL: insertps_from_broadcast_loadv4f32:
+; X32: ## %bb.0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; X32-NEXT: retl
+;
+; X64-LABEL: insertps_from_broadcast_loadv4f32:
+; X64: ## %bb.0:
+; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; X64-NEXT: retq
%1 = load <4 x float>, <4 x float>* %b, align 4
%2 = extractelement <4 x float> %1, i32 0
%3 = insertelement <4 x float> undef, float %2, i32 0
@@ -105,20 +147,32 @@ define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float
;; FIXME: We're emitting an extraneous pshufd/vbroadcast.
define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* nocapture readonly %fb, i64 %index) {
-; CHECK-LABEL: insertps_from_broadcast_multiple_use:
; On X32, account for the arguments' move to registers
-; X32: movl 8(%esp), %eax
-; X32: movl 4(%esp), %ecx
-; CHECK: vbroadcastss
-; CHECK-NOT: mov
-; CHECK: insertps $48
-; CHECK: insertps $48
-; CHECK: vaddps
-; CHECK: insertps $48
-; CHECK: insertps $48
-; CHECK: vaddps
-; CHECK: vaddps
-; CHECK-NEXT: ret
+; X32-LABEL: insertps_from_broadcast_multiple_use:
+; X32: ## %bb.0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT: vbroadcastss (%ecx,%eax,4), %xmm4
+; X32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
+; X32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
+; X32-NEXT: vaddps %xmm1, %xmm0, %xmm0
+; X32-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm4[0]
+; X32-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0,1,2],xmm4[0]
+; X32-NEXT: vaddps %xmm2, %xmm1, %xmm1
+; X32-NEXT: vaddps %xmm1, %xmm0, %xmm0
+; X32-NEXT: retl
+;
+; X64-LABEL: insertps_from_broadcast_multiple_use:
+; X64: ## %bb.0:
+; X64-NEXT: vbroadcastss (%rdi,%rsi,4), %xmm4
+; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
+; X64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
+; X64-NEXT: vaddps %xmm1, %xmm0, %xmm0
+; X64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm4[0]
+; X64-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0,1,2],xmm4[0]
+; X64-NEXT: vaddps %xmm2, %xmm1, %xmm1
+; X64-NEXT: vaddps %xmm1, %xmm0, %xmm0
+; X64-NEXT: retq
%1 = getelementptr inbounds float, float* %fb, i64 %index
%2 = load float, float* %1, align 4
%3 = insertelement <4 x float> undef, float %2, i32 0
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