[PATCH] D106561: [AArch64] Optimise min/max lowering in ISel

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7132
+  SDValue Cond = DAG.getSetCC(DL, VT, Op0, Op1, CC);
+  return DAG.getSelect(DL, VT, Cond, Op0, Op1);
+}
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If I'm understanding correctly, if we mark both ISD::SMAX and ISD::VSELECT as "Expand", vector legalization decides to unroll it.  So we mark ISD::SMAX as "Custom", then explicitly lower to a VSELECT to get the code we want.

This seems kind of silly, given VSELECT is equivalent to AArch64ISD::BSP.  For the sake of making changes to target-independent code easier, maybe we should consider marking ISD::VSELECT "custom"?  Or add a target hook to indicate whether the operation is cheap?


Repository:
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  https://reviews.llvm.org/D106561/new/

https://reviews.llvm.org/D106561