[llvm] 6e8660a - [NFC][PowerPC] Fix spe.ll to work with update_llc_test_checks.py again
Jessica Clarke via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 28 09:13:12 PDT 2021
Author: Jessica Clarke
Date: 2021-07-28T17:13:05+01:00
New Revision: 6e8660a7d65a30e3abcb4c588047c1328ab7d28e
URL: https://github.com/llvm/llvm-project/commit/6e8660a7d65a30e3abcb4c588047c1328ab7d28e
DIFF: https://github.com/llvm/llvm-project/commit/6e8660a7d65a30e3abcb4c588047c1328ab7d28e.diff
LOG: [NFC][PowerPC] Fix spe.ll to work with update_llc_test_checks.py again
Using split-file does not work with update_llc_test_checks.py. It's also
mostly redundant, as the single and double tests can just use a single
llc and FileCheck invocation for each FPU type using -check-prefixes
rather than -check-prefix, and update_llc_test_checks.py will merge what
it can. Only test_dasmconst needs to be SPE-only and so is pulled out
into its own mall file (rather than using sed to preprocess the file and
keep it commented out for EFPU2, which would work, but is ugly).
As well as cutting down on the number of RUN lines, this also results in
test_fma's CHECK lines being merged for both FPUs.
Reviewed By: kiausch
Differential Revision: https://reviews.llvm.org/D106969
Added:
llvm/test/CodeGen/PowerPC/spe-hwdouble.ll
Modified:
llvm/test/CodeGen/PowerPC/spe.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/spe-hwdouble.ll b/llvm/test/CodeGen/PowerPC/spe-hwdouble.ll
new file mode 100644
index 0000000000000..e004878afe68a
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/spe-hwdouble.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mattr=+spe | FileCheck %s
+
+define i32 @test_dasmconst(double %x) #0 {
+; CHECK-LABEL: test_dasmconst:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stwu 1, -16(1)
+; CHECK-NEXT: evmergelo 3, 3, 4
+; CHECK-NEXT: evstdd 3, 8(1)
+; CHECK-NEXT: #APP
+; CHECK-NEXT: efdctsi 3, 3
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: addi 1, 1, 16
+; CHECK-NEXT: blr
+entry:
+ %x.addr = alloca double, align 8
+ store double %x, double* %x.addr, align 8
+ %0 = load double, double* %x.addr, align 8
+ %1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
+ ret i32 %1
+}
+attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/PowerPC/spe.ll b/llvm/test/CodeGen/PowerPC/spe.ll
index 6ab05554aa818..fa7966db905ba 100644
--- a/llvm/test/CodeGen/PowerPC/spe.ll
+++ b/llvm/test/CodeGen/PowerPC/spe.ll
@@ -1,17 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: split-file %s %t
-; RUN: llc -verify-machineinstrs < %t/single.ll -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mattr=+spe | FileCheck %t/single.ll
-; RUN: llc -verify-machineinstrs < %t/double.ll -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mattr=+spe | FileCheck %t/double.ll -check-prefix=SPE
-; RUN: llc -verify-machineinstrs < %t/hwdouble.ll -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mattr=+spe | FileCheck %t/hwdouble.ll -check-prefix=SPE
-; RUN: llc -verify-machineinstrs < %t/single.ll -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mattr=+efpu2 | FileCheck %t/single.ll
-; RUN: llc -verify-machineinstrs < %t/double.ll -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mattr=+efpu2 | FileCheck %t/double.ll -check-prefix=EFPU2
-
-;--- single.ll
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mattr=+spe | FileCheck %s -check-prefixes=CHECK,SPE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -mattr=+efpu2 | FileCheck %s -check-prefixes=CHECK,EFPU2
+
; single tests (identical for -mattr=+spe and -mattr=+efpu2)
declare float @llvm.fabs.float(float)
@@ -542,7 +534,6 @@ entry:
}
attributes #0 = { nounwind }
-;--- double.ll
; Double tests
; results depend on -mattr=+spe or -mattr=+efpu2
@@ -772,11 +763,11 @@ define i1 @test_dcmpuno(double %a, double %b) #0 {
; SPE-NEXT: efdcmpeq 0, 3, 3
; SPE-NEXT: efdcmpeq 1, 5, 5
; SPE-NEXT: crand 20, 5, 1
-; SPE-NEXT: bc 12, 20, .LBB9_2
+; SPE-NEXT: bc 12, 20, .LBB35_2
; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0
; SPE-NEXT: blr
-; SPE-NEXT: .LBB9_2: # %entry
+; SPE-NEXT: .LBB35_2: # %entry
; SPE-NEXT: li 3, 0
; SPE-NEXT: blr
;
@@ -807,11 +798,11 @@ define i1 @test_dcmpord(double %a, double %b) #0 {
; SPE-NEXT: efdcmpeq 0, 4, 4
; SPE-NEXT: efdcmpeq 1, 3, 3
; SPE-NEXT: crnand 20, 5, 1
-; SPE-NEXT: bc 12, 20, .LBB10_2
+; SPE-NEXT: bc 12, 20, .LBB36_2
; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0
; SPE-NEXT: blr
-; SPE-NEXT: .LBB10_2: # %entry
+; SPE-NEXT: .LBB36_2: # %entry
; SPE-NEXT: li 3, 0
; SPE-NEXT: blr
;
@@ -839,13 +830,13 @@ define i32 @test_dcmpgt(double %a, double %b) #0 {
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmpgt 0, 3, 5
-; SPE-NEXT: ble 0, .LBB11_2
+; SPE-NEXT: ble 0, .LBB37_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: b .LBB11_3
-; SPE-NEXT: .LBB11_2: # %fa
+; SPE-NEXT: b .LBB37_3
+; SPE-NEXT: .LBB37_2: # %fa
; SPE-NEXT: li 3, 0
-; SPE-NEXT: .LBB11_3: # %ret
+; SPE-NEXT: .LBB37_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16
@@ -858,13 +849,13 @@ define i32 @test_dcmpgt(double %a, double %b) #0 {
; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __gtdf2
; EFPU2-NEXT: cmpwi 3, 1
-; EFPU2-NEXT: blt 0, .LBB11_2
+; EFPU2-NEXT: blt 0, .LBB37_2
; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1
-; EFPU2-NEXT: b .LBB11_3
-; EFPU2-NEXT: .LBB11_2: # %fa
+; EFPU2-NEXT: b .LBB37_3
+; EFPU2-NEXT: .LBB37_2: # %fa
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: .LBB11_3: # %ret
+; EFPU2-NEXT: .LBB37_3: # %ret
; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1)
@@ -893,19 +884,19 @@ define i32 @test_dcmpugt(double %a, double %b) #0 {
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: evmergelo 4, 5, 6
; SPE-NEXT: efdcmpeq 0, 4, 4
-; SPE-NEXT: bc 4, 1, .LBB12_4
+; SPE-NEXT: bc 4, 1, .LBB38_4
; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: efdcmpeq 0, 3, 3
-; SPE-NEXT: bc 4, 1, .LBB12_4
+; SPE-NEXT: bc 4, 1, .LBB38_4
; SPE-NEXT: # %bb.2: # %entry
; SPE-NEXT: efdcmpgt 0, 3, 4
-; SPE-NEXT: bc 12, 1, .LBB12_4
+; SPE-NEXT: bc 12, 1, .LBB38_4
; SPE-NEXT: # %bb.3: # %fa
; SPE-NEXT: li 3, 0
-; SPE-NEXT: b .LBB12_5
-; SPE-NEXT: .LBB12_4: # %tr
+; SPE-NEXT: b .LBB38_5
+; SPE-NEXT: .LBB38_4: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: .LBB12_5: # %ret
+; SPE-NEXT: .LBB38_5: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16
@@ -918,13 +909,13 @@ define i32 @test_dcmpugt(double %a, double %b) #0 {
; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __ledf2
; EFPU2-NEXT: cmpwi 3, 1
-; EFPU2-NEXT: blt 0, .LBB12_2
+; EFPU2-NEXT: blt 0, .LBB38_2
; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1
-; EFPU2-NEXT: b .LBB12_3
-; EFPU2-NEXT: .LBB12_2: # %fa
+; EFPU2-NEXT: b .LBB38_3
+; EFPU2-NEXT: .LBB38_2: # %fa
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: .LBB12_3: # %ret
+; EFPU2-NEXT: .LBB38_3: # %ret
; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1)
@@ -953,13 +944,13 @@ define i32 @test_dcmple(double %a, double %b) #0 {
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmpgt 0, 3, 5
-; SPE-NEXT: bgt 0, .LBB13_2
+; SPE-NEXT: bgt 0, .LBB39_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: b .LBB13_3
-; SPE-NEXT: .LBB13_2: # %fa
+; SPE-NEXT: b .LBB39_3
+; SPE-NEXT: .LBB39_2: # %fa
; SPE-NEXT: li 3, 0
-; SPE-NEXT: .LBB13_3: # %ret
+; SPE-NEXT: .LBB39_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16
@@ -972,13 +963,13 @@ define i32 @test_dcmple(double %a, double %b) #0 {
; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __gtdf2
; EFPU2-NEXT: cmpwi 3, 0
-; EFPU2-NEXT: bgt 0, .LBB13_2
+; EFPU2-NEXT: bgt 0, .LBB39_2
; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1
-; EFPU2-NEXT: b .LBB13_3
-; EFPU2-NEXT: .LBB13_2: # %fa
+; EFPU2-NEXT: b .LBB39_3
+; EFPU2-NEXT: .LBB39_2: # %fa
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: .LBB13_3: # %ret
+; EFPU2-NEXT: .LBB39_3: # %ret
; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1)
@@ -1007,13 +998,13 @@ define i32 @test_dcmpule(double %a, double %b) #0 {
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmpgt 0, 3, 5
-; SPE-NEXT: bgt 0, .LBB14_2
+; SPE-NEXT: bgt 0, .LBB40_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: b .LBB14_3
-; SPE-NEXT: .LBB14_2: # %fa
+; SPE-NEXT: b .LBB40_3
+; SPE-NEXT: .LBB40_2: # %fa
; SPE-NEXT: li 3, 0
-; SPE-NEXT: .LBB14_3: # %ret
+; SPE-NEXT: .LBB40_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16
@@ -1026,13 +1017,13 @@ define i32 @test_dcmpule(double %a, double %b) #0 {
; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __gtdf2
; EFPU2-NEXT: cmpwi 3, 0
-; EFPU2-NEXT: bgt 0, .LBB14_2
+; EFPU2-NEXT: bgt 0, .LBB40_2
; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1
-; EFPU2-NEXT: b .LBB14_3
-; EFPU2-NEXT: .LBB14_2: # %fa
+; EFPU2-NEXT: b .LBB40_3
+; EFPU2-NEXT: .LBB40_2: # %fa
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: .LBB14_3: # %ret
+; EFPU2-NEXT: .LBB40_3: # %ret
; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1)
@@ -1062,13 +1053,13 @@ define i32 @test_dcmpeq(double %a, double %b) #0 {
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmpeq 0, 3, 5
-; SPE-NEXT: ble 0, .LBB15_2
+; SPE-NEXT: ble 0, .LBB41_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: b .LBB15_3
-; SPE-NEXT: .LBB15_2: # %fa
+; SPE-NEXT: b .LBB41_3
+; SPE-NEXT: .LBB41_2: # %fa
; SPE-NEXT: li 3, 0
-; SPE-NEXT: .LBB15_3: # %ret
+; SPE-NEXT: .LBB41_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16
@@ -1081,13 +1072,13 @@ define i32 @test_dcmpeq(double %a, double %b) #0 {
; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __nedf2
; EFPU2-NEXT: cmplwi 3, 0
-; EFPU2-NEXT: bne 0, .LBB15_2
+; EFPU2-NEXT: bne 0, .LBB41_2
; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1
-; EFPU2-NEXT: b .LBB15_3
-; EFPU2-NEXT: .LBB15_2: # %fa
+; EFPU2-NEXT: b .LBB41_3
+; EFPU2-NEXT: .LBB41_2: # %fa
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: .LBB15_3: # %ret
+; EFPU2-NEXT: .LBB41_3: # %ret
; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1)
@@ -1116,16 +1107,16 @@ define i32 @test_dcmpueq(double %a, double %b) #0 {
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmplt 0, 3, 5
-; SPE-NEXT: bc 12, 1, .LBB16_3
+; SPE-NEXT: bc 12, 1, .LBB42_3
; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: efdcmpgt 0, 3, 5
-; SPE-NEXT: bc 12, 1, .LBB16_3
+; SPE-NEXT: bc 12, 1, .LBB42_3
; SPE-NEXT: # %bb.2: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: b .LBB16_4
-; SPE-NEXT: .LBB16_3: # %fa
+; SPE-NEXT: b .LBB42_4
+; SPE-NEXT: .LBB42_3: # %fa
; SPE-NEXT: li 3, 0
-; SPE-NEXT: .LBB16_4: # %ret
+; SPE-NEXT: .LBB42_4: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16
@@ -1157,16 +1148,16 @@ define i32 @test_dcmpueq(double %a, double %b) #0 {
; EFPU2-NEXT: mr 5, 29
; EFPU2-NEXT: mr 6, 30
; EFPU2-NEXT: bl __unorddf2
-; EFPU2-NEXT: bc 12, 10, .LBB16_3
+; EFPU2-NEXT: bc 12, 10, .LBB42_3
; EFPU2-NEXT: # %bb.1: # %entry
; EFPU2-NEXT: cmpwi 3, 0
-; EFPU2-NEXT: bc 4, 2, .LBB16_3
+; EFPU2-NEXT: bc 4, 2, .LBB42_3
; EFPU2-NEXT: # %bb.2: # %fa
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: b .LBB16_4
-; EFPU2-NEXT: .LBB16_3: # %tr
+; EFPU2-NEXT: b .LBB42_4
+; EFPU2-NEXT: .LBB42_3: # %tr
; EFPU2-NEXT: li 3, 1
-; EFPU2-NEXT: .LBB16_4: # %ret
+; EFPU2-NEXT: .LBB42_4: # %ret
; EFPU2-NEXT: stw 3, 20(1)
; EFPU2-NEXT: lwz 3, 20(1)
; EFPU2-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
@@ -1207,11 +1198,11 @@ define i1 @test_dcmpne(double %a, double %b) #0 {
; SPE-NEXT: efdcmplt 0, 3, 5
; SPE-NEXT: efdcmpgt 1, 3, 5
; SPE-NEXT: crnor 20, 5, 1
-; SPE-NEXT: bc 12, 20, .LBB17_2
+; SPE-NEXT: bc 12, 20, .LBB43_2
; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0
; SPE-NEXT: blr
-; SPE-NEXT: .LBB17_2: # %entry
+; SPE-NEXT: .LBB43_2: # %entry
; SPE-NEXT: li 3, 0
; SPE-NEXT: blr
;
@@ -1248,13 +1239,13 @@ define i1 @test_dcmpne(double %a, double %b) #0 {
; EFPU2-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
; EFPU2-NEXT: crorc 20, 2, 10
; EFPU2-NEXT: lwz 12, 72(1)
-; EFPU2-NEXT: bc 12, 20, .LBB17_2
+; EFPU2-NEXT: bc 12, 20, .LBB43_2
; EFPU2-NEXT: # %bb.1: # %entry
; EFPU2-NEXT: ori 3, 4, 0
-; EFPU2-NEXT: b .LBB17_3
-; EFPU2-NEXT: .LBB17_2: # %entry
+; EFPU2-NEXT: b .LBB43_3
+; EFPU2-NEXT: .LBB43_2: # %entry
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: .LBB17_3: # %entry
+; EFPU2-NEXT: .LBB43_3: # %entry
; EFPU2-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
; EFPU2-NEXT: mtcrf 32, 12 # cr2
; EFPU2-NEXT: lwz 30, 88(1) # 4-byte Folded Reload
@@ -1277,13 +1268,13 @@ define i32 @test_dcmpune(double %a, double %b) #0 {
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmpeq 0, 3, 5
-; SPE-NEXT: bgt 0, .LBB18_2
+; SPE-NEXT: bgt 0, .LBB44_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: b .LBB18_3
-; SPE-NEXT: .LBB18_2: # %fa
+; SPE-NEXT: b .LBB44_3
+; SPE-NEXT: .LBB44_2: # %fa
; SPE-NEXT: li 3, 0
-; SPE-NEXT: .LBB18_3: # %ret
+; SPE-NEXT: .LBB44_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16
@@ -1296,13 +1287,13 @@ define i32 @test_dcmpune(double %a, double %b) #0 {
; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __eqdf2
; EFPU2-NEXT: cmplwi 3, 0
-; EFPU2-NEXT: beq 0, .LBB18_2
+; EFPU2-NEXT: beq 0, .LBB44_2
; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1
-; EFPU2-NEXT: b .LBB18_3
-; EFPU2-NEXT: .LBB18_2: # %fa
+; EFPU2-NEXT: b .LBB44_3
+; EFPU2-NEXT: .LBB44_2: # %fa
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: .LBB18_3: # %ret
+; EFPU2-NEXT: .LBB44_3: # %ret
; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1)
@@ -1331,13 +1322,13 @@ define i32 @test_dcmplt(double %a, double %b) #0 {
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmplt 0, 3, 5
-; SPE-NEXT: ble 0, .LBB19_2
+; SPE-NEXT: ble 0, .LBB45_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: b .LBB19_3
-; SPE-NEXT: .LBB19_2: # %fa
+; SPE-NEXT: b .LBB45_3
+; SPE-NEXT: .LBB45_2: # %fa
; SPE-NEXT: li 3, 0
-; SPE-NEXT: .LBB19_3: # %ret
+; SPE-NEXT: .LBB45_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16
@@ -1350,13 +1341,13 @@ define i32 @test_dcmplt(double %a, double %b) #0 {
; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __ltdf2
; EFPU2-NEXT: cmpwi 3, -1
-; EFPU2-NEXT: bgt 0, .LBB19_2
+; EFPU2-NEXT: bgt 0, .LBB45_2
; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1
-; EFPU2-NEXT: b .LBB19_3
-; EFPU2-NEXT: .LBB19_2: # %fa
+; EFPU2-NEXT: b .LBB45_3
+; EFPU2-NEXT: .LBB45_2: # %fa
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: .LBB19_3: # %ret
+; EFPU2-NEXT: .LBB45_3: # %ret
; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1)
@@ -1385,19 +1376,19 @@ define i32 @test_dcmpult(double %a, double %b) #0 {
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: evmergelo 4, 5, 6
; SPE-NEXT: efdcmpeq 0, 4, 4
-; SPE-NEXT: bc 4, 1, .LBB20_4
+; SPE-NEXT: bc 4, 1, .LBB46_4
; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: efdcmpeq 0, 3, 3
-; SPE-NEXT: bc 4, 1, .LBB20_4
+; SPE-NEXT: bc 4, 1, .LBB46_4
; SPE-NEXT: # %bb.2: # %entry
; SPE-NEXT: efdcmplt 0, 3, 4
-; SPE-NEXT: bc 12, 1, .LBB20_4
+; SPE-NEXT: bc 12, 1, .LBB46_4
; SPE-NEXT: # %bb.3: # %fa
; SPE-NEXT: li 3, 0
-; SPE-NEXT: b .LBB20_5
-; SPE-NEXT: .LBB20_4: # %tr
+; SPE-NEXT: b .LBB46_5
+; SPE-NEXT: .LBB46_4: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: .LBB20_5: # %ret
+; SPE-NEXT: .LBB46_5: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16
@@ -1410,13 +1401,13 @@ define i32 @test_dcmpult(double %a, double %b) #0 {
; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __gedf2
; EFPU2-NEXT: cmpwi 3, -1
-; EFPU2-NEXT: bgt 0, .LBB20_2
+; EFPU2-NEXT: bgt 0, .LBB46_2
; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1
-; EFPU2-NEXT: b .LBB20_3
-; EFPU2-NEXT: .LBB20_2: # %fa
+; EFPU2-NEXT: b .LBB46_3
+; EFPU2-NEXT: .LBB46_2: # %fa
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: .LBB20_3: # %ret
+; EFPU2-NEXT: .LBB46_3: # %ret
; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1)
@@ -1449,11 +1440,11 @@ define i1 @test_dcmpge(double %a, double %b) #0 {
; SPE-NEXT: efdcmplt 5, 3, 4
; SPE-NEXT: crand 24, 5, 1
; SPE-NEXT: crorc 20, 21, 24
-; SPE-NEXT: bc 12, 20, .LBB21_2
+; SPE-NEXT: bc 12, 20, .LBB47_2
; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0
; SPE-NEXT: blr
-; SPE-NEXT: .LBB21_2: # %entry
+; SPE-NEXT: .LBB47_2: # %entry
; SPE-NEXT: li 3, 0
; SPE-NEXT: blr
;
@@ -1481,13 +1472,13 @@ define i32 @test_dcmpuge(double %a, double %b) #0 {
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmplt 0, 3, 5
-; SPE-NEXT: bgt 0, .LBB22_2
+; SPE-NEXT: bgt 0, .LBB48_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: b .LBB22_3
-; SPE-NEXT: .LBB22_2: # %fa
+; SPE-NEXT: b .LBB48_3
+; SPE-NEXT: .LBB48_2: # %fa
; SPE-NEXT: li 3, 0
-; SPE-NEXT: .LBB22_3: # %ret
+; SPE-NEXT: .LBB48_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16
@@ -1500,13 +1491,13 @@ define i32 @test_dcmpuge(double %a, double %b) #0 {
; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __ltdf2
; EFPU2-NEXT: cmpwi 3, 0
-; EFPU2-NEXT: blt 0, .LBB22_2
+; EFPU2-NEXT: blt 0, .LBB48_2
; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1
-; EFPU2-NEXT: b .LBB22_3
-; EFPU2-NEXT: .LBB22_2: # %fa
+; EFPU2-NEXT: b .LBB48_3
+; EFPU2-NEXT: .LBB48_2: # %fa
; EFPU2-NEXT: li 3, 0
-; EFPU2-NEXT: .LBB22_3: # %ret
+; EFPU2-NEXT: .LBB48_3: # %ret
; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1)
@@ -1534,10 +1525,10 @@ define double @test_dselect(double %a, double %b, i1 %c) #0 {
; SPE-NEXT: andi. 7, 7, 1
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 4, 3, 4
-; SPE-NEXT: bc 12, 1, .LBB23_2
+; SPE-NEXT: bc 12, 1, .LBB49_2
; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: evor 4, 5, 5
-; SPE-NEXT: .LBB23_2: # %entry
+; SPE-NEXT: .LBB49_2: # %entry
; SPE-NEXT: evmergehi 3, 4, 4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
@@ -1650,13 +1641,9 @@ entry:
declare double @test_spill_spe_regs(double, double);
define dso_local void @test_func2() #0 {
-; SPE-LABEL: test_func2:
-; SPE: # %bb.0: # %entry
-; SPE-NEXT: blr
-;
-; EFPU2-LABEL: test_func2:
-; EFPU2: # %bb.0: # %entry
-; EFPU2-NEXT: blr
+; CHECK-LABEL: test_func2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: blr
entry:
ret void
}
@@ -1673,8 +1660,8 @@ define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32*
; SPE-NEXT: evstddx 30, 1, 5 # 8-byte Folded Spill
; SPE-NEXT: li 5, 264
; SPE-NEXT: evstddx 31, 1, 5 # 8-byte Folded Spill
-; SPE-NEXT: li 5, .LCPI29_0 at l
-; SPE-NEXT: lis 6, .LCPI29_0 at ha
+; SPE-NEXT: li 5, .LCPI55_0 at l
+; SPE-NEXT: lis 6, .LCPI55_0 at ha
; SPE-NEXT: evlddx 5, 6, 5
; SPE-NEXT: stw 14, 280(1) # 4-byte Folded Spill
; SPE-NEXT: stw 15, 284(1) # 4-byte Folded Spill
@@ -1852,81 +1839,43 @@ return:
}
define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 {
-; SPE-LABEL: test_fma:
-; SPE: # %bb.0: # %entry
-; SPE-NEXT: mflr 0
-; SPE-NEXT: stw 0, 4(1)
-; SPE-NEXT: stwu 1, -48(1)
-; SPE-NEXT: cmpwi 3, 1
-; SPE-NEXT: stw 29, 36(1) # 4-byte Folded Spill
-; SPE-NEXT: stw 30, 40(1) # 4-byte Folded Spill
-; SPE-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill
-; SPE-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
-; SPE-NEXT: blt 0, .LBB30_3
-; SPE-NEXT: # %bb.1: # %for.body.preheader
-; SPE-NEXT: mr 30, 3
-; SPE-NEXT: li 29, 0
-; SPE-NEXT: # implicit-def: $r5
-; SPE-NEXT: .LBB30_2: # %for.body
-; SPE-NEXT: #
-; SPE-NEXT: efscfsi 3, 29
-; SPE-NEXT: mr 4, 3
-; SPE-NEXT: bl fmaf
-; SPE-NEXT: addi 29, 29, 1
-; SPE-NEXT: cmplw 30, 29
-; SPE-NEXT: mr 5, 3
-; SPE-NEXT: bne 0, .LBB30_2
-; SPE-NEXT: b .LBB30_4
-; SPE-NEXT: .LBB30_3:
-; SPE-NEXT: # implicit-def: $r5
-; SPE-NEXT: .LBB30_4: # %for.cond.cleanup
-; SPE-NEXT: evldd 30, 16(1) # 8-byte Folded Reload
-; SPE-NEXT: mr 3, 5
-; SPE-NEXT: evldd 29, 8(1) # 8-byte Folded Reload
-; SPE-NEXT: lwz 30, 40(1) # 4-byte Folded Reload
-; SPE-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
-; SPE-NEXT: lwz 0, 52(1)
-; SPE-NEXT: addi 1, 1, 48
-; SPE-NEXT: mtlr 0
-; SPE-NEXT: blr
-;
-; EFPU2-LABEL: test_fma:
-; EFPU2: # %bb.0: # %entry
-; EFPU2-NEXT: mflr 0
-; EFPU2-NEXT: stw 0, 4(1)
-; EFPU2-NEXT: stwu 1, -48(1)
-; EFPU2-NEXT: cmpwi 3, 1
-; EFPU2-NEXT: stw 29, 36(1) # 4-byte Folded Spill
-; EFPU2-NEXT: stw 30, 40(1) # 4-byte Folded Spill
-; EFPU2-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill
-; EFPU2-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
-; EFPU2-NEXT: blt 0, .LBB30_3
-; EFPU2-NEXT: # %bb.1: # %for.body.preheader
-; EFPU2-NEXT: mr 30, 3
-; EFPU2-NEXT: li 29, 0
-; EFPU2-NEXT: # implicit-def: $r5
-; EFPU2-NEXT: .LBB30_2: # %for.body
-; EFPU2-NEXT: #
-; EFPU2-NEXT: efscfsi 3, 29
-; EFPU2-NEXT: mr 4, 3
-; EFPU2-NEXT: bl fmaf
-; EFPU2-NEXT: addi 29, 29, 1
-; EFPU2-NEXT: cmplw 30, 29
-; EFPU2-NEXT: mr 5, 3
-; EFPU2-NEXT: bne 0, .LBB30_2
-; EFPU2-NEXT: b .LBB30_4
-; EFPU2-NEXT: .LBB30_3:
-; EFPU2-NEXT: # implicit-def: $r5
-; EFPU2-NEXT: .LBB30_4: # %for.cond.cleanup
-; EFPU2-NEXT: evldd 30, 16(1) # 8-byte Folded Reload
-; EFPU2-NEXT: mr 3, 5
-; EFPU2-NEXT: evldd 29, 8(1) # 8-byte Folded Reload
-; EFPU2-NEXT: lwz 30, 40(1) # 4-byte Folded Reload
-; EFPU2-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
-; EFPU2-NEXT: lwz 0, 52(1)
-; EFPU2-NEXT: addi 1, 1, 48
-; EFPU2-NEXT: mtlr 0
-; EFPU2-NEXT: blr
+; CHECK-LABEL: test_fma:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stw 0, 4(1)
+; CHECK-NEXT: stwu 1, -48(1)
+; CHECK-NEXT: cmpwi 3, 1
+; CHECK-NEXT: stw 29, 36(1) # 4-byte Folded Spill
+; CHECK-NEXT: stw 30, 40(1) # 4-byte Folded Spill
+; CHECK-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill
+; CHECK-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
+; CHECK-NEXT: blt 0, .LBB56_3
+; CHECK-NEXT: # %bb.1: # %for.body.preheader
+; CHECK-NEXT: mr 30, 3
+; CHECK-NEXT: li 29, 0
+; CHECK-NEXT: # implicit-def: $r5
+; CHECK-NEXT: .LBB56_2: # %for.body
+; CHECK-NEXT: #
+; CHECK-NEXT: efscfsi 3, 29
+; CHECK-NEXT: mr 4, 3
+; CHECK-NEXT: bl fmaf
+; CHECK-NEXT: addi 29, 29, 1
+; CHECK-NEXT: cmplw 30, 29
+; CHECK-NEXT: mr 5, 3
+; CHECK-NEXT: bne 0, .LBB56_2
+; CHECK-NEXT: b .LBB56_4
+; CHECK-NEXT: .LBB56_3:
+; CHECK-NEXT: # implicit-def: $r5
+; CHECK-NEXT: .LBB56_4: # %for.cond.cleanup
+; CHECK-NEXT: evldd 30, 16(1) # 8-byte Folded Reload
+; CHECK-NEXT: mr 3, 5
+; CHECK-NEXT: evldd 29, 8(1) # 8-byte Folded Reload
+; CHECK-NEXT: lwz 30, 40(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 0, 52(1)
+; CHECK-NEXT: addi 1, 1, 48
+; CHECK-NEXT: mtlr 0
+; CHECK-NEXT: blr
entry:
%cmp8 = icmp sgt i32 %d, 0
br i1 %cmp8, label %for.body, label %for.cond.cleanup
@@ -2061,25 +2010,3 @@ entry:
ret void
}
attributes #0 = { nounwind }
-
-;--- hwdouble.ll
-; split into separate file because the efd* instructions are invalid on efpu2
-define i32 @test_dasmconst(double %x) #0 {
-; SPE-LABEL: test_dasmconst:
-; SPE: # %bb.0: # %entry
-; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: evstdd 3, 8(1)
-; SPE-NEXT: #APP
-; SPE-NEXT: efdctsi 3, 3
-; SPE-NEXT: #NO_APP
-; SPE-NEXT: addi 1, 1, 16
-; SPE-NEXT: blr
-entry:
- %x.addr = alloca double, align 8
- store double %x, double* %x.addr, align 8
- %0 = load double, double* %x.addr, align 8
- %1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
- ret i32 %1
-}
-attributes #0 = { nounwind }
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