[PATCH] D105130: [RISCV] Enable interleaved access vectorization

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

If we aren't using segment load/store, what does the backend codegen for this look like?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105130/new/

https://reviews.llvm.org/D105130