[PATCH] D106729: [AMDGPU] Support non-strictly stronger memory orderings in SIMemoryLegalizer
Tony Tye via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 27 03:35:00 PDT 2021
t-tye added a comment.
In D106729#2904861 <https://reviews.llvm.org/D106729#2904861>, @efriedma wrote:
> No testcases?
Added tests.
================
Comment at: llvm/include/llvm/Support/AtomicOrdering.h:136
+/// Return a single atomic ordering that is at least as strong as both the \p A0
+/// and \p Other orderings for an atomic operation.
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foad wrote:
> Typo "A0" for "AO".
Corrected.
================
Comment at: llvm/include/llvm/Support/AtomicOrdering.h:140-141
+ AtomicOrdering Other) {
+ if (((AO == AtomicOrdering::Acquire) && (Other == AtomicOrdering::Release)) ||
+ ((AO == AtomicOrdering::Release) && (Other == AtomicOrdering::Acquire)))
+ return AtomicOrdering::AcquireRelease;
----------------
foad wrote:
> You don't need any of these innermost parentheses.
Removed innermost parenthesis.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106729/new/
https://reviews.llvm.org/D106729
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