[PATCH] D106651: [RISCV] Add support for vector saturating add/sub operations
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 27 02:13:32 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG172487fe4c67: [RISCV] Add support for vector saturating add/sub operations (authored by frasercrmck).
Changed prior to commit:
https://reviews.llvm.org/D106651?vs=361158&id=361948#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106651/new/
https://reviews.llvm.org/D106651
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
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