[PATCH] D98002: [RISCV] Add scheduling resources for V

[Evandro Menezes via Phabricator via llvm-commits]

evandro marked an inline comment as done.
evandro added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:701
+
+multiclass VSALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+  def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
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frasercrmck wrote:
> Do the saturating instructions need resources for `VXSAT`/`VXRM`?
It doesn't seem to me that sideband registers needs must be modeled for scheduling.


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https://reviews.llvm.org/D98002