[PATCH] D106549: [AArch64][SVE] Combine bitcasts to predicate types with vector inserts of loads

[JunMa via Phabricator via llvm-commits]

junparser added inline comments.


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Comment at: llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp:294
+    std::tie(MinSVEVectorSize, MaxSVEVectorSize) = Attr.getVScaleRangeArgs();
+    if (MinSVEVectorSize != MaxSVEVectorSize && MaxSVEVectorSize != 0)
+      continue;
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Why do we disable differing vscale min/max? I donot see any difference between vscale_range(4,0) and vscale_range(4,6).


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D106549/new/

https://reviews.llvm.org/D106549