[PATCH] D94097: [AArch64] Legalize MVT::i64x8 in DAG isel lowering.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp:347
+    if (OpInfo.ConstraintVT == MVT::i64x8)
+      return false;
+
----------------
It's a little unfortunate we're sticking this in target-independent code, but not sure there's a better place.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:251
+    addRegisterClass(MVT::i64x8, &AArch64::GPR64x8ClassRegClass);
+    setOperationAction(ISD::BITCAST, MVT::i64x8, Legal);
+    setOperationAction(ISD::UNDEF, MVT::i64x8, Legal);
----------------
Not sure why you're marking BITCAST Legal; there isn't any legal type to bitcast from.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:254
+    setOperationAction(ISD::LOAD, MVT::i64x8, Custom);
+    setOperationAction(ISD::STORE, MVT::i64x8, Custom);
+  }
----------------
I guess LOAD/STORE come out of type legalization?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94097/new/

https://reviews.llvm.org/D94097