[llvm] c658b47 - [GlobalISel] Add a constant folding combine.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 26 14:53:52 PDT 2021
Author: Amara Emerson
Date: 2021-07-26T14:53:33-07:00
New Revision: c658b472f3e61e1818e1909bf02f3d65470018a5
URL: https://github.com/llvm/llvm-project/commit/c658b472f3e61e1818e1909bf02f3d65470018a5
DIFF: https://github.com/llvm/llvm-project/commit/c658b472f3e61e1818e1909bf02f3d65470018a5.diff
LOG: [GlobalISel] Add a constant folding combine.
Use it AArch64 post-legal combiner. These don't always get folded because when
the instructions are created the constants are obscured by artifacts.
Differential Revision: https://reviews.llvm.org/D106776
Added:
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir
Modified:
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
llvm/include/llvm/Target/GlobalISel/Combine.td
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/lib/Target/AArch64/AArch64Combine.td
llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
llvm/test/CodeGen/AArch64/fold-global-offsets.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 9005a6eb62ab2..56459b68dce08 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -384,6 +384,9 @@ class CombinerHelper {
/// Replace an instruction with a G_CONSTANT with value \p C.
bool replaceInstWithConstant(MachineInstr &MI, int64_t C);
+ /// Replace an instruction with a G_CONSTANT with value \p C.
+ bool replaceInstWithConstant(MachineInstr &MI, APInt C);
+
/// Replace an instruction with a G_IMPLICIT_DEF.
bool replaceInstWithUndef(MachineInstr &MI);
@@ -543,6 +546,10 @@ class CombinerHelper {
bool matchReassocPtrAdd(MachineInstr &MI,
std::function<void(MachineIRBuilder &)> &MatchInfo);
+
+ /// Do constant folding when opportunities are exposed after MIR building.
+ bool matchConstantFold(MachineInstr &MI, APInt &MatchInfo);
+
/// Try to transform \p MI by using all of the above
/// combine functions. Returns true if changed.
bool tryCombine(MachineInstr &MI);
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 9704091701497..f35156d598492 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -115,6 +115,7 @@ class GIApplyKindWithArgs;
def register_matchinfo: GIDefMatchData<"Register">;
def int64_matchinfo: GIDefMatchData<"int64_t">;
+def apint_matchinfo : GIDefMatchData<"APInt">;
def build_fn_matchinfo :
GIDefMatchData<"std::function<void(MachineIRBuilder &)>">;
@@ -661,6 +662,13 @@ def reassoc_ptradd : GICombineRule<
def reassocs : GICombineGroup<[reassoc_ptradd]>;
+// Constant fold operations.
+def constant_fold : GICombineRule<
+ (defs root:$d, apint_matchinfo:$matchinfo),
+ (match (wip_match_opcode G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR):$d,
+ [{ return Helper.matchConstantFold(*${d}, ${matchinfo}); }]),
+ (apply [{ Helper.replaceInstWithConstant(*${d}, ${matchinfo}); }])>;
+
// FIXME: These should use the custom predicate feature once it lands.
def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
undef_to_negative_one,
@@ -705,7 +713,8 @@ def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shl,
const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
- div_rem_to_divrem, funnel_shift_combines, form_bitfield_extract]>;
+ div_rem_to_divrem, funnel_shift_combines, form_bitfield_extract,
+ constant_fold]>;
// A combine group used to for prelegalizer combiners at -O0. The combines in
// this group have been selected based on experiments to balance code size and
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 0e07bc43ebd4c..06d827de2e96b 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2807,6 +2807,14 @@ bool CombinerHelper::replaceInstWithConstant(MachineInstr &MI, int64_t C) {
return true;
}
+bool CombinerHelper::replaceInstWithConstant(MachineInstr &MI, APInt C) {
+ assert(MI.getNumDefs() == 1 && "Expected only one def?");
+ Builder.setInstr(MI);
+ Builder.buildConstant(MI.getOperand(0), C);
+ MI.eraseFromParent();
+ return true;
+}
+
bool CombinerHelper::replaceInstWithUndef(MachineInstr &MI) {
assert(MI.getNumDefs() == 1 && "Expected only one def?");
Builder.setInstr(MI);
@@ -4246,6 +4254,16 @@ bool CombinerHelper::matchReassocPtrAdd(
return !reassociationCanBreakAddressingModePattern(MI);
}
+bool CombinerHelper::matchConstantFold(MachineInstr &MI, APInt &MatchInfo) {
+ Register Op1 = MI.getOperand(1).getReg();
+ Register Op2 = MI.getOperand(2).getReg();
+ auto MaybeCst = ConstantFoldBinOp(MI.getOpcode(), Op1, Op2, MRI);
+ if (!MaybeCst)
+ return false;
+ MatchInfo = *MaybeCst;
+ return true;
+}
+
bool CombinerHelper::tryCombine(MachineInstr &MI) {
if (tryCombineCopy(MI))
return true;
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 7f9b2fe815274..f562beb613ede 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -211,6 +211,7 @@ def AArch64PostLegalizerCombinerHelper
mul_const, redundant_sext_inreg,
form_bitfield_extract, rotate_out_of_range,
icmp_to_true_false_known_bits, merge_unmerge,
- select_combines, fold_merge_to_zext]> {
+ select_combines, fold_merge_to_zext,
+ constant_fold]> {
let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
index 7830ad05e1ac1..c8c032dfdc285 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
@@ -347,34 +347,30 @@ define void @val_compare_and_swap_monotonic(i128* %p, i128 %oldval, i128 %newval
define void @atomic_load_relaxed(i64, i64, i128* %p, i128* %p2) {
; CHECK-LLSC-O1-LABEL: atomic_load_relaxed:
; CHECK-LLSC-O1: // %bb.0:
-; CHECK-LLSC-O1-NEXT: mov w8, #64
-; CHECK-LLSC-O1-NEXT: sub x9, x8, #64 // =64
; CHECK-LLSC-O1-NEXT: .LBB4_1: // %atomicrmw.start
; CHECK-LLSC-O1-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-LLSC-O1-NEXT: ldxp x10, x8, [x2]
-; CHECK-LLSC-O1-NEXT: lsl x8, x8, x9
-; CHECK-LLSC-O1-NEXT: lsr x11, x8, x9
-; CHECK-LLSC-O1-NEXT: stxp w12, x10, x11, [x2]
-; CHECK-LLSC-O1-NEXT: cbnz w12, .LBB4_1
+; CHECK-LLSC-O1-NEXT: ldxp x9, x8, [x2]
+; CHECK-LLSC-O1-NEXT: lsr x8, x8, #0
+; CHECK-LLSC-O1-NEXT: lsr x10, x8, #0
+; CHECK-LLSC-O1-NEXT: stxp w11, x9, x10, [x2]
+; CHECK-LLSC-O1-NEXT: cbnz w11, .LBB4_1
; CHECK-LLSC-O1-NEXT: // %bb.2: // %atomicrmw.end
-; CHECK-LLSC-O1-NEXT: mov v0.d[0], x10
+; CHECK-LLSC-O1-NEXT: mov v0.d[0], x9
; CHECK-LLSC-O1-NEXT: mov v0.d[1], x8
; CHECK-LLSC-O1-NEXT: str q0, [x3]
; CHECK-LLSC-O1-NEXT: ret
;
; CHECK-CAS-O1-LABEL: atomic_load_relaxed:
; CHECK-CAS-O1: // %bb.0:
-; CHECK-CAS-O1-NEXT: mov w8, #64
-; CHECK-CAS-O1-NEXT: sub x9, x8, #64 // =64
; CHECK-CAS-O1-NEXT: .LBB4_1: // %atomicrmw.start
; CHECK-CAS-O1-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-CAS-O1-NEXT: ldxp x10, x8, [x2]
-; CHECK-CAS-O1-NEXT: lsl x8, x8, x9
-; CHECK-CAS-O1-NEXT: lsr x11, x8, x9
-; CHECK-CAS-O1-NEXT: stxp w12, x10, x11, [x2]
-; CHECK-CAS-O1-NEXT: cbnz w12, .LBB4_1
+; CHECK-CAS-O1-NEXT: ldxp x9, x8, [x2]
+; CHECK-CAS-O1-NEXT: lsr x8, x8, #0
+; CHECK-CAS-O1-NEXT: lsr x10, x8, #0
+; CHECK-CAS-O1-NEXT: stxp w11, x9, x10, [x2]
+; CHECK-CAS-O1-NEXT: cbnz w11, .LBB4_1
; CHECK-CAS-O1-NEXT: // %bb.2: // %atomicrmw.end
-; CHECK-CAS-O1-NEXT: mov v0.d[0], x10
+; CHECK-CAS-O1-NEXT: mov v0.d[0], x9
; CHECK-CAS-O1-NEXT: mov v0.d[1], x8
; CHECK-CAS-O1-NEXT: str q0, [x3]
; CHECK-CAS-O1-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir
new file mode 100644
index 0000000000000..d5b2b9fa0502a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir
@@ -0,0 +1,129 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: add
+alignment: 4
+legalized: true
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.1.entry:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: add
+ ; CHECK: %res:_(s64) = G_CONSTANT i64 42
+ ; CHECK: $x0 = COPY %res(s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %a:_(s64) = G_CONSTANT i64 40
+ %b:_(s64) = G_CONSTANT i64 2
+ %res:_(s64) = G_ADD %a, %b
+ $x0 = COPY %res(s64)
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: sub
+alignment: 4
+legalized: true
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.1.entry:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: sub
+ ; CHECK: %res:_(s64) = G_CONSTANT i64 38
+ ; CHECK: $x0 = COPY %res(s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %a:_(s64) = G_CONSTANT i64 40
+ %b:_(s64) = G_CONSTANT i64 2
+ %res:_(s64) = G_SUB %a, %b
+ $x0 = COPY %res(s64)
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: mul
+alignment: 4
+legalized: true
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.1.entry:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: mul
+ ; CHECK: %res:_(s64) = G_CONSTANT i64 80
+ ; CHECK: $x0 = COPY %res(s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %a:_(s64) = G_CONSTANT i64 40
+ %b:_(s64) = G_CONSTANT i64 2
+ %res:_(s64) = G_MUL %a, %b
+ $x0 = COPY %res(s64)
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: and
+alignment: 4
+legalized: true
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.1.entry:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: and
+ ; CHECK: %res:_(s64) = G_CONSTANT i64 0
+ ; CHECK: $x0 = COPY %res(s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %a:_(s64) = G_CONSTANT i64 40
+ %b:_(s64) = G_CONSTANT i64 2
+ %res:_(s64) = G_AND %a, %b
+ $x0 = COPY %res(s64)
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: or
+alignment: 4
+legalized: true
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.1.entry:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: or
+ ; CHECK: %res:_(s64) = G_CONSTANT i64 62
+ ; CHECK: $x0 = COPY %res(s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %a:_(s64) = G_CONSTANT i64 42
+ %b:_(s64) = G_CONSTANT i64 22
+ %res:_(s64) = G_OR %a, %b
+ $x0 = COPY %res(s64)
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: xor
+alignment: 4
+legalized: true
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.1.entry:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: xor
+ ; CHECK: %res:_(s64) = G_CONSTANT i64 12
+ ; CHECK: $x0 = COPY %res(s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %a:_(s64) = G_CONSTANT i64 8
+ %b:_(s64) = G_CONSTANT i64 4
+ %res:_(s64) = G_XOR %a, %b
+ $x0 = COPY %res(s64)
+ RET_ReallyLR implicit $x0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/fold-global-offsets.ll b/llvm/test/CodeGen/AArch64/fold-global-offsets.ll
index 1871cc3caf3e7..f98c52770d29c 100644
--- a/llvm/test/CodeGen/AArch64/fold-global-offsets.ll
+++ b/llvm/test/CodeGen/AArch64/fold-global-offsets.ll
@@ -131,11 +131,9 @@ define i32 @f7() {
; GISEL-NEXT: adrp x8, x3+88
; GISEL-NEXT: add x8, x8, :lo12:x3+88
; GISEL-NEXT: mov v0.d[1], x8
-; GISEL-NEXT: mov w9, #64
; GISEL-NEXT: mov d0, v0.d[1]
-; GISEL-NEXT: sub x8, x9, #64 // =64
-; GISEL-NEXT: fmov x9, d0
-; GISEL-NEXT: lsr x8, x9, x8
+; GISEL-NEXT: fmov x8, d0
+; GISEL-NEXT: lsr x8, x8, #0
; GISEL-NEXT: ldr w0, [x8, #20]
; GISEL-NEXT: ret
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index e852f9a4a4c18..7ad60a5a7f7fc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -9,15 +9,14 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX6: ; %bb.0:
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_sub_i32 s3, 0, 7
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX6-NEXT: s_movk_i32 s3, 0x7f
; GFX6-NEXT: s_and_b32 s2, s2, s3
; GFX6-NEXT: s_and_b32 s1, s1, s3
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_lshr_b32 s1, s1, 1
+; GFX6-NEXT: v_mul_lo_u32 v1, -7, v0
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX6-NEXT: v_mul_lo_u32 v0, v0, 7
@@ -41,16 +40,15 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX8: ; %bb.0:
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: s_sub_i32 s3, 0, 7
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX8-NEXT: s_movk_i32 s3, 0x7f
; GFX8-NEXT: s_and_b32 s2, s2, s3
; GFX8-NEXT: s_and_b32 s1, s1, s3
-; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshr_b32 s1, s1, 1
+; GFX8-NEXT: v_mul_lo_u32 v1, -7, v0
+; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX8-NEXT: v_mul_lo_u32 v0, v0, 7
@@ -74,16 +72,15 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s3, 0, 7
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX9-NEXT: s_movk_i32 s3, 0x7f
; GFX9-NEXT: s_and_b32 s2, s2, s3
; GFX9-NEXT: s_and_b32 s1, s1, s3
-; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX9-NEXT: s_lshr_b32 s1, s1, 1
+; GFX9-NEXT: v_mul_lo_u32 v1, -7, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX9-NEXT: v_mul_lo_u32 v0, v0, 7
@@ -106,17 +103,16 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX10-LABEL: s_fshl_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
-; GFX10-NEXT: s_sub_i32 s3, 0, 7
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX10-NEXT: s_movk_i32 s3, 0x7f
; GFX10-NEXT: s_and_b32 s2, s2, s3
; GFX10-NEXT: s_and_b32 s1, s1, s3
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX10-NEXT: s_lshr_b32 s1, s1, 1
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-NEXT: v_mul_lo_u32 v1, -7, v0
+; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX10-NEXT: v_mul_lo_u32 v0, v0, 7
@@ -145,11 +141,10 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX6-NEXT: s_sub_i32 s4, 0, 7
; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX6-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -177,11 +172,10 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX8-NEXT: s_sub_i32 s4, 0, 7
; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX8-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX8-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -209,11 +203,10 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX9-NEXT: s_sub_i32 s4, 0, 7
; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -241,14 +234,13 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
-; GFX10-NEXT: s_sub_i32 s4, 0, 7
; GFX10-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX10-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: v_lshrrev_b16 v1, 1, v1
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX10-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX10-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX10-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -1216,15 +1208,15 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX6: ; %bb.0:
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_sub_i32 s3, 0, 24
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX6-NEXT: s_mov_b32 s3, 0xffffff
; GFX6-NEXT: s_and_b32 s2, s2, s3
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_and_b32 s1, s1, s3
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: s_lshr_b32 s1, s1, 1
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, v0
+; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
@@ -1248,15 +1240,15 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX8: ; %bb.0:
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: s_sub_i32 s3, 0, 24
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX8-NEXT: s_mov_b32 s3, 0xffffff
; GFX8-NEXT: s_and_b32 s2, s2, s3
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s1, s1, s3
-; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: s_lshr_b32 s1, s1, 1
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, v0
+; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
@@ -1280,15 +1272,15 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s3, 0, 24
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX9-NEXT: s_mov_b32 s3, 0xffffff
; GFX9-NEXT: s_and_b32 s2, s2, s3
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s1, s1, s3
-; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: s_lshr_b32 s1, s1, 1
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
@@ -1310,15 +1302,14 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX10-LABEL: s_fshl_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX10-NEXT: s_sub_i32 s3, 0, 24
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_lo_u32 v1, s3, v0
; GFX10-NEXT: s_mov_b32 s3, 0xffffff
; GFX10-NEXT: s_and_b32 s2, s2, s3
; GFX10-NEXT: s_and_b32 s1, s1, s3
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_lshr_b32 s1, s1, 1
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-NEXT: v_mul_lo_u32 v1, 0xffffffe8, v0
; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_hi_u32 v0, s2, v0
@@ -1347,11 +1338,11 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX6-NEXT: s_sub_i32 s4, 0, 24
+; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffffe8
; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX6-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -1379,11 +1370,11 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX8-NEXT: s_sub_i32 s4, 0, 24
+; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffffe8
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX8-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX8-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -1411,11 +1402,11 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX9-NEXT: s_sub_i32 s4, 0, 24
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffffe8
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -1442,12 +1433,11 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
-; GFX10-NEXT: s_sub_i32 s4, 0, 24
; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX10-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX10-NEXT: v_mul_lo_u32 v4, 0xffffffe8, v3
; GFX10-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffffff
@@ -1478,11 +1468,13 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_movk_i32 s9, 0xff
; GFX6-NEXT: s_mov_b32 s11, 0x80008
; GFX6-NEXT: s_lshr_b32 s6, s0, 16
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX6-NEXT: s_lshr_b32 s7, s0, 24
; GFX6-NEXT: s_and_b32 s10, s0, s9
; GFX6-NEXT: s_bfe_u32 s0, s0, s11
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_and_b32 s6, s6, s9
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_or_b32 s0, s10, s0
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX6-NEXT: s_lshr_b32 s8, s1, 8
@@ -1493,9 +1485,11 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_or_b32 s0, s0, s6
; GFX6-NEXT: s_and_b32 s6, s8, s9
; GFX6-NEXT: s_or_b32 s1, s7, s1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: s_or_b32 s1, s1, s6
; GFX6-NEXT: s_lshr_b32 s6, s2, 16
; GFX6-NEXT: s_lshr_b32 s7, s2, 24
@@ -1505,8 +1499,8 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_and_b32 s6, s6, s9
; GFX6-NEXT: s_or_b32 s2, s10, s2
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xffffffe8
+; GFX6-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX6-NEXT: s_lshr_b32 s8, s3, 8
; GFX6-NEXT: s_and_b32 s3, s3, s9
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
@@ -1518,7 +1512,7 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_or_b32 s3, s3, s6
; GFX6-NEXT: s_lshr_b32 s6, s4, 16
; GFX6-NEXT: s_lshr_b32 s7, s4, 24
@@ -1526,82 +1520,76 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_bfe_u32 s4, s4, s11
; GFX6-NEXT: s_lshl_b32 s4, s4, 8
; GFX6-NEXT: s_and_b32 s6, s6, s9
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_or_b32 s4, s10, s4
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_or_b32 s4, s4, s6
-; GFX6-NEXT: s_sub_i32 s6, 0, 24
-; GFX6-NEXT: v_mul_lo_u32 v1, s6, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_lshr_b32 s8, s5, 8
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX6-NEXT: s_and_b32 s5, s5, s9
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v0
; GFX6-NEXT: s_lshl_b32 s5, s5, 8
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: s_and_b32 s6, s8, s9
; GFX6-NEXT: s_or_b32 s5, s7, s5
-; GFX6-NEXT: s_and_b32 s7, s8, s9
-; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX6-NEXT: s_lshl_b32 s7, s7, 16
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: s_lshl_b32 s6, s6, 16
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: s_or_b32 s5, s5, s6
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX6-NEXT: s_mov_b32 s6, 0xffffff
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v1
+; GFX6-NEXT: v_and_b32_e32 v1, s6, v1
; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX6-NEXT: s_or_b32 s5, s5, s7
-; GFX6-NEXT: s_mov_b32 s7, 0xffffff
-; GFX6-NEXT: v_mul_lo_u32 v3, s6, v1
-; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_lshl_b32_e32 v1, s0, v1
+; GFX6-NEXT: s_lshr_b32 s0, s2, 1
+; GFX6-NEXT: v_and_b32_e32 v2, s6, v3
+; GFX6-NEXT: v_lshr_b32_e32 v2, s0, v2
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v0
-; GFX6-NEXT: v_and_b32_e32 v0, s7, v0
-; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX6-NEXT: s_lshr_b32 s0, s2, 1
-; GFX6-NEXT: v_and_b32_e32 v2, s7, v2
-; GFX6-NEXT: v_lshr_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v1
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v0
+; GFX6-NEXT: v_and_b32_e32 v0, v0, v4
; GFX6-NEXT: s_lshr_b32 s0, s3, 1
; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX6-NEXT: v_bfe_u32 v3, v0, 8, 8
-; GFX6-NEXT: v_lshl_b32_e32 v1, s1, v1
+; GFX6-NEXT: v_bfe_u32 v3, v1, 8, 8
+; GFX6-NEXT: v_lshl_b32_e32 v0, s1, v0
; GFX6-NEXT: v_lshr_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s9, v0
-; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_bfe_u32 v2, v1, 8, 8
+; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_and_b32_e32 v2, s9, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX6-NEXT: v_bfe_u32 v2, v0, 8, 8
+; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v1
+; GFX6-NEXT: v_readfirstlane_b32 s1, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fshl_v2i24:
@@ -1622,117 +1610,115 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_lshl_b32 s1, s1, s11
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_and_b32 s6, s9, s10
; GFX8-NEXT: s_or_b32 s1, s8, s1
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_or_b32 s1, s1, s6
; GFX8-NEXT: s_lshr_b32 s6, s2, 8
; GFX8-NEXT: s_and_b32 s6, s6, s10
+; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX8-NEXT: s_lshr_b32 s7, s2, 16
; GFX8-NEXT: s_lshr_b32 s8, s2, 24
; GFX8-NEXT: s_and_b32 s2, s2, s10
; GFX8-NEXT: s_lshl_b32 s6, s6, s11
; GFX8-NEXT: s_or_b32 s2, s2, s6
; GFX8-NEXT: s_and_b32 s6, s7, s10
+; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX8-NEXT: s_lshr_b32 s9, s3, 8
; GFX8-NEXT: s_and_b32 s3, s3, s10
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_lshl_b32 s3, s3, s11
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX8-NEXT: s_or_b32 s2, s2, s6
; GFX8-NEXT: s_and_b32 s6, s9, s10
+; GFX8-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX8-NEXT: s_or_b32 s3, s8, s3
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_or_b32 s3, s3, s6
; GFX8-NEXT: s_lshr_b32 s6, s4, 8
; GFX8-NEXT: s_and_b32 s6, s6, s10
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_lshr_b32 s7, s4, 16
; GFX8-NEXT: s_lshr_b32 s8, s4, 24
; GFX8-NEXT: s_and_b32 s4, s4, s10
; GFX8-NEXT: s_lshl_b32 s6, s6, s11
; GFX8-NEXT: s_or_b32 s4, s4, s6
; GFX8-NEXT: s_and_b32 s6, s7, s10
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_or_b32 s4, s4, s6
-; GFX8-NEXT: s_sub_i32 s6, 0, 24
-; GFX8-NEXT: v_mul_lo_u32 v1, s6, v0
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
+; GFX8-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_lshr_b32 s9, s5, 8
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX8-NEXT: s_and_b32 s5, s5, s10
+; GFX8-NEXT: v_mul_lo_u32 v2, v2, v0
; GFX8-NEXT: s_lshl_b32 s5, s5, s11
-; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX8-NEXT: s_and_b32 s7, s9, s10
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s4, v1
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: s_and_b32 s6, s9, s10
; GFX8-NEXT: s_or_b32 s5, s8, s5
-; GFX8-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT: s_lshl_b32 s7, s7, 16
-; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX8-NEXT: s_lshl_b32 s6, s6, 16
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: s_or_b32 s5, s5, s6
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX8-NEXT: s_mov_b32 s6, 0xffffff
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v1
+; GFX8-NEXT: v_and_b32_e32 v1, s6, v1
; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX8-NEXT: s_or_b32 s5, s5, s7
-; GFX8-NEXT: s_mov_b32 s7, 0xffffff
-; GFX8-NEXT: v_mul_lo_u32 v3, s6, v1
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
+; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s0
+; GFX8-NEXT: s_lshr_b32 s0, s2, 1
+; GFX8-NEXT: v_and_b32_e32 v2, s6, v3
+; GFX8-NEXT: v_lshrrev_b32_e64 v2, v2, s0
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s5, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
-; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v0
-; GFX8-NEXT: v_and_b32_e32 v0, s7, v0
-; GFX8-NEXT: v_lshlrev_b32_e64 v0, v0, s0
-; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX8-NEXT: s_lshr_b32 s0, s2, 1
-; GFX8-NEXT: v_and_b32_e32 v2, s7, v2
-; GFX8-NEXT: v_lshrrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v1
-; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v0
+; GFX8-NEXT: v_and_b32_e32 v0, v0, v4
; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
; GFX8-NEXT: s_lshr_b32 s0, s3, 1
-; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s1
+; GFX8-NEXT: v_lshlrev_b32_e64 v0, v0, s1
; GFX8-NEXT: v_lshrrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_mov_b32_e32 v2, 8
-; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX8-NEXT: v_mov_b32_e32 v4, 16
-; GFX8-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
-; GFX8-NEXT: v_and_b32_e32 v3, s10, v1
-; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_sdwa v3, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX8-NEXT: v_and_b32_e32 v3, s10, v0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX8-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v1
+; GFX8-NEXT: v_readfirstlane_b32 s1, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fshl_v2i24:
@@ -1753,21 +1739,25 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s13
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: s_or_b32 s0, s0, s7
; GFX9-NEXT: s_and_b32 s7, s11, s12
; GFX9-NEXT: s_or_b32 s1, s10, s1
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_or_b32 s1, s1, s7
; GFX9-NEXT: s_lshr_b32 s7, s2, 8
; GFX9-NEXT: s_and_b32 s7, s7, s12
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX9-NEXT: s_lshr_b32 s9, s2, 16
; GFX9-NEXT: s_lshr_b32 s10, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, s12
; GFX9-NEXT: s_lshl_b32 s7, s7, s13
; GFX9-NEXT: s_or_b32 s2, s2, s7
; GFX9-NEXT: s_and_b32 s7, s9, s12
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX9-NEXT: s_lshr_b32 s11, s3, 8
; GFX9-NEXT: s_and_b32 s3, s3, s12
@@ -1776,221 +1766,212 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_or_b32 s2, s2, s7
; GFX9-NEXT: s_and_b32 s7, s11, s12
; GFX9-NEXT: s_lshl_b32 s3, s3, s13
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX9-NEXT: s_or_b32 s3, s10, s3
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: s_or_b32 s3, s3, s7
; GFX9-NEXT: s_lshr_b32 s7, s4, 8
; GFX9-NEXT: s_and_b32 s7, s7, s12
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: s_lshr_b32 s9, s4, 16
; GFX9-NEXT: s_lshr_b32 s10, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, s12
; GFX9-NEXT: s_lshl_b32 s7, s7, s13
; GFX9-NEXT: s_or_b32 s4, s4, s7
; GFX9-NEXT: s_and_b32 s7, s9, s12
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v0
; GFX9-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_or_b32 s4, s4, s7
-; GFX9-NEXT: s_sub_i32 s7, 0, 24
-; GFX9-NEXT: v_mul_lo_u32 v1, s7, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX9-NEXT: s_lshr_b32 s11, s5, 8
; GFX9-NEXT: s_and_b32 s5, s5, s12
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_lshl_b32 s5, s5, s13
-; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX9-NEXT: s_and_b32 s9, s11, s12
+; GFX9-NEXT: s_and_b32 s7, s11, s12
; GFX9-NEXT: s_or_b32 s5, s10, s5
-; GFX9-NEXT: s_bfe_u32 s9, s9, 0x100000
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX9-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX9-NEXT: s_lshl_b32 s9, s9, 16
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_lshl_b32 s7, s7, 16
+; GFX9-NEXT: s_or_b32 s5, s5, s7
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX9-NEXT: s_or_b32 s5, s5, s9
-; GFX9-NEXT: s_mov_b32 s9, 0xffffff
-; GFX9-NEXT: v_mul_lo_u32 v3, s7, v1
-; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
-; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v0
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: s_mov_b32 s7, 0xffffff
+; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
+; GFX9-NEXT: s_lshr_b32 s2, s2, 1
+; GFX9-NEXT: v_and_b32_e32 v3, s7, v3
+; GFX9-NEXT: v_sub_u32_e32 v0, s5, v0
+; GFX9-NEXT: v_and_b32_e32 v1, s7, v1
+; GFX9-NEXT: v_lshrrev_b32_e64 v3, v3, s2
+; GFX9-NEXT: v_lshl_or_b32 v1, s0, v1, v3
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT: v_sub_u32_e32 v2, 23, v0
-; GFX9-NEXT: s_lshr_b32 s2, s2, 1
-; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX9-NEXT: v_and_b32_e32 v2, s9, v2
-; GFX9-NEXT: v_and_b32_e32 v0, s9, v0
-; GFX9-NEXT: v_lshrrev_b32_e64 v2, v2, s2
-; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, s0, v0, v2
-; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xffffff
-; GFX9-NEXT: v_sub_u32_e32 v2, 23, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffff
+; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
+; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
; GFX9-NEXT: s_lshr_b32 s0, s3, 1
-; GFX9-NEXT: v_and_b32_e32 v2, v2, v3
-; GFX9-NEXT: v_and_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_and_b32_e32 v2, v3, v2
; GFX9-NEXT: v_lshrrev_b32_e64 v2, v2, s0
-; GFX9-NEXT: v_lshl_or_b32 v1, s1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, s1, v0, v2
; GFX9-NEXT: s_mov_b32 s6, 8
-; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX9-NEXT: v_and_b32_e32 v3, s12, v1
+; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX9-NEXT: v_and_b32_e32 v3, s12, v0
; GFX9-NEXT: s_mov_b32 s8, 16
-; GFX9-NEXT: v_and_or_b32 v2, v0, s12, v2
-; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX9-NEXT: v_and_or_b32 v2, v1, s12, v2
+; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX9-NEXT: v_or3_b32 v0, v2, v0, v3
-; GFX9-NEXT: v_bfe_u32 v2, v1, 8, 8
-; GFX9-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 8, v2
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_or3_b32 v1, v2, v1, v3
+; GFX9-NEXT: v_bfe_u32 v2, v0, 8, 8
+; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v1
+; GFX9-NEXT: v_readfirstlane_b32 s1, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_fshl_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
-; GFX10-NEXT: s_sub_i32 s14, 0, 24
; GFX10-NEXT: s_movk_i32 s9, 0xff
-; GFX10-NEXT: s_lshr_b32 s10, s1, 8
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX10-NEXT: s_bfe_u32 s11, 8, 0x100000
+; GFX10-NEXT: s_lshr_b32 s11, s1, 8
+; GFX10-NEXT: s_bfe_u32 s10, 8, 0x100000
; GFX10-NEXT: s_and_b32 s1, s1, s9
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_lshr_b32 s6, s0, 8
; GFX10-NEXT: s_lshr_b32 s8, s0, 24
-; GFX10-NEXT: s_lshl_b32 s1, s1, s11
+; GFX10-NEXT: s_lshl_b32 s1, s1, s10
; GFX10-NEXT: s_and_b32 s6, s6, s9
; GFX10-NEXT: s_or_b32 s1, s8, s1
; GFX10-NEXT: s_lshr_b32 s8, s4, 8
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX10-NEXT: s_and_b32 s8, s8, s9
; GFX10-NEXT: s_lshr_b32 s7, s0, 16
+; GFX10-NEXT: s_and_b32 s8, s8, s9
; GFX10-NEXT: s_and_b32 s0, s0, s9
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: s_lshl_b32 s6, s6, s11
+; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX10-NEXT: s_lshl_b32 s6, s6, s10
; GFX10-NEXT: s_lshr_b32 s12, s4, 24
; GFX10-NEXT: s_or_b32 s0, s0, s6
-; GFX10-NEXT: v_mul_lo_u32 v2, s14, v0
-; GFX10-NEXT: v_mul_lo_u32 v3, s14, v1
+; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: s_and_b32 s6, s7, s9
-; GFX10-NEXT: s_and_b32 s7, s10, s9
-; GFX10-NEXT: s_lshr_b32 s10, s4, 16
+; GFX10-NEXT: s_and_b32 s7, s11, s9
+; GFX10-NEXT: s_lshr_b32 s11, s4, 16
+; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v1
+; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v0
; GFX10-NEXT: s_and_b32 s4, s4, s9
-; GFX10-NEXT: s_lshl_b32 s8, s8, s11
+; GFX10-NEXT: s_lshl_b32 s8, s8, s10
; GFX10-NEXT: s_lshr_b32 s13, s5, 8
-; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: s_or_b32 s4, s4, s8
-; GFX10-NEXT: s_and_b32 s8, s10, s9
-; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX10-NEXT: s_bfe_u32 s8, s8, 0x100000
+; GFX10-NEXT: s_and_b32 s8, s11, s9
; GFX10-NEXT: s_and_b32 s5, s5, s9
+; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
+; GFX10-NEXT: v_mul_hi_u32 v3, v0, v3
+; GFX10-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX10-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX10-NEXT: s_lshl_b32 s8, s8, 16
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
-; GFX10-NEXT: s_lshl_b32 s5, s5, s11
+; GFX10-NEXT: s_lshl_b32 s5, s5, s10
; GFX10-NEXT: s_or_b32 s4, s4, s8
; GFX10-NEXT: s_and_b32 s8, s13, s9
+; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: s_or_b32 s5, s12, s5
; GFX10-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX10-NEXT: v_mul_hi_u32 v0, s4, v0
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v3
; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
+; GFX10-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX10-NEXT: s_lshl_b32 s8, s8, 16
-; GFX10-NEXT: s_lshr_b32 s10, s2, 16
+; GFX10-NEXT: s_lshr_b32 s11, s2, 16
; GFX10-NEXT: s_or_b32 s5, s5, s8
; GFX10-NEXT: s_lshr_b32 s8, s2, 8
-; GFX10-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX10-NEXT: v_mul_hi_u32 v0, s5, v0
; GFX10-NEXT: s_and_b32 s8, s8, s9
; GFX10-NEXT: s_and_b32 s12, s2, s9
-; GFX10-NEXT: s_lshl_b32 s8, s8, s11
-; GFX10-NEXT: s_and_b32 s10, s10, s9
+; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX10-NEXT: s_lshl_b32 s8, s8, s10
+; GFX10-NEXT: s_and_b32 s11, s11, s9
; GFX10-NEXT: s_or_b32 s8, s12, s8
; GFX10-NEXT: s_lshr_b32 s2, s2, 24
-; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, s4, v0
-; GFX10-NEXT: s_bfe_u32 s4, s8, 0x100000
-; GFX10-NEXT: s_bfe_u32 s8, s10, 0x100000
+; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX10-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX10-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, s5, v1
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, s4, v1
+; GFX10-NEXT: s_bfe_u32 s4, s8, 0x100000
+; GFX10-NEXT: s_bfe_u32 s8, s11, 0x100000
+; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
+; GFX10-NEXT: s_lshl_b32 s6, s6, 16
+; GFX10-NEXT: v_sub_nc_u32_e32 v0, s5, v0
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_lshl_b32 s5, s8, 16
; GFX10-NEXT: s_lshr_b32 s8, s3, 8
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
; GFX10-NEXT: s_and_b32 s3, s3, s9
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
-; GFX10-NEXT: s_lshl_b32 s3, s3, s11
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
+; GFX10-NEXT: s_lshl_b32 s3, s3, s10
; GFX10-NEXT: s_or_b32 s4, s4, s5
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
; GFX10-NEXT: s_or_b32 s2, s2, s3
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_and_b32 s3, s8, s9
; GFX10-NEXT: s_mov_b32 s5, 0xffffff
; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX10-NEXT: s_lshl_b32 s3, s3, 16
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, 23, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
+; GFX10-NEXT: v_sub_nc_u32_e32 v2, 23, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffffff
; GFX10-NEXT: s_or_b32 s2, s2, s3
; GFX10-NEXT: s_lshr_b32 s3, s4, 1
; GFX10-NEXT: v_and_b32_e32 v2, s5, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v1
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v0
; GFX10-NEXT: s_lshr_b32 s2, s2, 1
-; GFX10-NEXT: v_and_b32_e32 v0, s5, v0
-; GFX10-NEXT: v_and_b32_e32 v1, v1, v3
+; GFX10-NEXT: v_and_b32_e32 v1, s5, v1
+; GFX10-NEXT: v_and_b32_e32 v0, v0, v3
; GFX10-NEXT: v_lshrrev_b32_e64 v2, v2, s3
; GFX10-NEXT: v_and_b32_e32 v4, v4, v3
-; GFX10-NEXT: s_lshl_b32 s6, s6, 16
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX10-NEXT: s_lshl_b32 s7, s7, 16
; GFX10-NEXT: s_or_b32 s0, s0, s6
-; GFX10-NEXT: v_lshrrev_b32_e64 v3, v4, s2
; GFX10-NEXT: s_or_b32 s1, s1, s7
-; GFX10-NEXT: v_lshl_or_b32 v0, s0, v0, v2
+; GFX10-NEXT: v_lshl_or_b32 v1, s0, v1, v2
+; GFX10-NEXT: v_lshrrev_b32_e64 v3, v4, s2
; GFX10-NEXT: s_mov_b32 s0, 8
-; GFX10-NEXT: v_lshl_or_b32 v1, s1, v1, v3
-; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX10-NEXT: v_lshl_or_b32 v0, s1, v0, v3
; GFX10-NEXT: s_mov_b32 s0, 16
-; GFX10-NEXT: v_and_b32_e32 v3, s9, v1
-; GFX10-NEXT: v_bfe_u32 v4, v1, 8, 8
-; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX10-NEXT: v_and_or_b32 v2, v0, s9, v2
-; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX10-NEXT: v_and_or_b32 v2, v1, s9, v2
+; GFX10-NEXT: v_and_b32_e32 v3, s9, v0
+; GFX10-NEXT: v_bfe_u32 v4, v0, 8, 8
+; GFX10-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v4
-; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v4
+; GFX10-NEXT: v_or3_b32 v1, v2, v1, v3
+; GFX10-NEXT: v_readfirstlane_b32 s1, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v1
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i48 %lhs.arg to <2 x i24>
%rhs = bitcast i48 %rhs.arg to <2 x i24>
@@ -2006,38 +1987,36 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX6-NEXT: s_sub_i32 s4, 0, 24
+; GFX6-NEXT: v_mov_b32_e32 v8, 0xffffffe8
; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v8, 24
+; GFX6-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
+; GFX6-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX6-NEXT: v_mul_lo_u32 v7, s4, v6
-; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v8
-; GFX6-NEXT: v_mov_b32_e32 v8, 0xffffff
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v8
-; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX6-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX6-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX6-NEXT: v_mul_lo_u32 v9, v8, v7
+; GFX6-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GFX6-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX6-NEXT: v_mov_b32_e32 v9, 0xffffff
+; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
+; GFX6-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v7
+; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, s4, v7
-; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 23, v4
-; GFX6-NEXT: v_and_b32_e32 v4, v4, v8
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX6-NEXT: v_mul_lo_u32 v7, v8, v6
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 23, v4
+; GFX6-NEXT: v_and_b32_e32 v4, v4, v9
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_mul_hi_u32 v6, v7, v6
-; GFX6-NEXT: v_and_b32_e32 v4, v5, v8
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v6
+; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7
+; GFX6-NEXT: v_and_b32_e32 v4, v5, v9
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v7
; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5
-; GFX6-NEXT: v_and_b32_e32 v6, v9, v8
+; GFX6-NEXT: v_and_b32_e32 v6, v8, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_mul_lo_u32 v5, v5, 24
@@ -2049,11 +2028,11 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v8
+; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_and_b32_e32 v2, v3, v8
+; GFX6-NEXT: v_and_b32_e32 v2, v3, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT: v_and_b32_e32 v3, v4, v8
+; GFX6-NEXT: v_and_b32_e32 v3, v4, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -2063,38 +2042,36 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX8-NEXT: s_sub_i32 s4, 0, 24
+; GFX8-NEXT: v_mov_b32_e32 v8, 0xffffffe8
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v8, 24
+; GFX8-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
+; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX8-NEXT: v_mul_lo_u32 v7, s4, v6
-; GFX8-NEXT: v_mul_hi_u32 v7, v6, v7
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
-; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v7, v8
-; GFX8-NEXT: v_mov_b32_e32 v8, 0xffffff
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v8
-; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX8-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX8-NEXT: v_mul_lo_u32 v9, v8, v7
+; GFX8-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9
+; GFX8-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX8-NEXT: v_mov_b32_e32 v9, 0xffffff
+; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6
-; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
+; GFX8-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v7
+; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT: v_mul_lo_u32 v6, s4, v7
-; GFX8-NEXT: v_sub_u32_e32 v9, vcc, 23, v4
-; GFX8-NEXT: v_and_b32_e32 v4, v4, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX8-NEXT: v_mul_lo_u32 v7, v8, v6
+; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 23, v4
+; GFX8-NEXT: v_and_b32_e32 v4, v4, v9
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX8-NEXT: v_mul_hi_u32 v6, v7, v6
-; GFX8-NEXT: v_and_b32_e32 v4, v5, v8
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v6
+; GFX8-NEXT: v_mul_hi_u32 v7, v6, v7
+; GFX8-NEXT: v_and_b32_e32 v4, v5, v9
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, v6, v7
; GFX8-NEXT: v_mul_hi_u32 v5, v4, v5
-; GFX8-NEXT: v_and_b32_e32 v6, v9, v8
+; GFX8-NEXT: v_and_b32_e32 v6, v8, v9
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_mul_lo_u32 v5, v5, 24
@@ -2106,11 +2083,11 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v8
+; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_and_b32_e32 v2, v3, v8
+; GFX8-NEXT: v_and_b32_e32 v2, v3, v9
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_and_b32_e32 v3, v4, v8
+; GFX8-NEXT: v_and_b32_e32 v3, v4, v9
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v3, v2
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -2120,43 +2097,39 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX9-NEXT: s_sub_i32 s4, 0, 24
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v8, 24
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, 0xffffffe8
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX9-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX9-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX9-NEXT: v_mul_lo_u32 v9, v8, v7
+; GFX9-NEXT: v_mul_lo_u32 v8, v8, v6
+; GFX9-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
+; GFX9-NEXT: v_mul_hi_u32 v7, v4, v7
; GFX9-NEXT: v_mov_b32_e32 v9, 0xffffff
-; GFX9-NEXT: v_mul_lo_u32 v7, s4, v6
; GFX9-NEXT: v_and_b32_e32 v5, v5, v9
+; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX9-NEXT: v_and_b32_e32 v2, v2, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_mul_hi_u32 v7, v6, v7
-; GFX9-NEXT: v_and_b32_e32 v3, v3, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3
-; GFX9-NEXT: v_add_u32_e32 v6, v6, v7
-; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v8
-; GFX9-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX9-NEXT: v_mul_lo_u32 v8, s4, v7
-; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX9-NEXT: v_mul_hi_u32 v8, v7, v8
-; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
-; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
+; GFX9-NEXT: v_sub_u32_e32 v4, v4, v7
+; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_add_u32_e32 v7, v7, v8
-; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX9-NEXT: v_sub_u32_e32 v6, 23, v4
-; GFX9-NEXT: v_and_b32_e32 v6, v6, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX9-NEXT: v_sub_u32_e32 v7, 23, v4
+; GFX9-NEXT: v_and_b32_e32 v7, v7, v9
; GFX9-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, v6, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, v7, v2
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v4, v2
-; GFX9-NEXT: v_sub_u32_e32 v2, v5, v7
+; GFX9-NEXT: v_sub_u32_e32 v2, v5, v6
; GFX9-NEXT: v_subrev_u32_e32 v4, 24, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2164,6 +2137,8 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_sub_u32_e32 v4, 23, v2
+; GFX9-NEXT: v_and_b32_e32 v3, v3, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3
; GFX9-NEXT: v_and_b32_e32 v4, v4, v9
; GFX9-NEXT: v_and_b32_e32 v2, v2, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v3, v4, v3
@@ -2175,33 +2150,30 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
-; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
-; GFX10-NEXT: s_sub_i32 s4, 0, 24
; GFX10-NEXT: v_mov_b32_e32 v10, 0xffffff
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX10-NEXT: v_and_b32_e32 v5, v5, v10
; GFX10-NEXT: v_and_b32_e32 v2, v2, v10
; GFX10-NEXT: v_and_b32_e32 v3, v3, v10
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v3
-; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
+; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
-; GFX10-NEXT: v_mul_lo_u32 v8, s4, v6
-; GFX10-NEXT: v_mul_lo_u32 v9, s4, v7
-; GFX10-NEXT: v_mul_hi_u32 v8, v6, v8
-; GFX10-NEXT: v_mul_hi_u32 v9, v7, v9
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v9
-; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
-; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v7
+; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v6
+; GFX10-NEXT: v_mul_hi_u32 v8, v7, v8
+; GFX10-NEXT: v_mul_hi_u32 v9, v6, v9
+; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v9
+; GFX10-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX10-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7
+; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v7
+; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v6
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
@@ -3421,31 +3393,25 @@ define <2 x i16> @v_fshl_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT: s_bfe_u32 s5, 11, 0x100000
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, s5, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 12, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: s_bfe_u32 s5, 8, 0x100000
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT: s_bfe_u32 s4, 7, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s5, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fshl_v2i16_4_8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 4, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, 11, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 12, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX8-NEXT: v_mov_b32_e32 v3, 1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v3, 8
; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v2
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, 7, v1
+; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: v_mov_b32_e32 v2, 16
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
@@ -3458,14 +3424,14 @@ define <2 x i16> @v_fshl_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, 16
; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 16
+; GFX9-NEXT: s_mov_b32 s4, 0x4f7ffffe
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX9-NEXT: s_sub_i32 s4, 0, 16
-; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX9-NEXT: v_mul_f32_e32 v2, s4, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, s4, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT: v_mul_lo_u32 v4, s4, v2
-; GFX9-NEXT: v_mul_lo_u32 v5, s4, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, -16, v2
+; GFX9-NEXT: v_mul_lo_u32 v5, -16, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
@@ -3503,15 +3469,15 @@ define <2 x i16> @v_fshl_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, 16
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 16
-; GFX10-NEXT: s_sub_i32 s4, 0, 16
+; GFX10-NEXT: s_mov_b32 s4, 0x4f7ffffe
; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX10-NEXT: v_mul_f32_e32 v2, s4, v2
+; GFX10-NEXT: v_mul_f32_e32 v3, s4, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX10-NEXT: v_mul_lo_u32 v4, s4, v2
-; GFX10-NEXT: v_mul_lo_u32 v5, s4, v3
+; GFX10-NEXT: v_mul_lo_u32 v4, -16, v2
+; GFX10-NEXT: v_mul_lo_u32 v5, -16, v3
; GFX10-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX10-NEXT: v_mul_hi_u32 v5, v3, v5
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v4
@@ -4707,44 +4673,44 @@ define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
; GFX6-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX6-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX6-NEXT: s_sub_i32 s9, s12, 64
-; GFX6-NEXT: s_sub_i32 s13, 64, s12
+; GFX6-NEXT: s_sub_i32 s10, 64, s12
; GFX6-NEXT: s_cmp_lt_u32 s12, 64
-; GFX6-NEXT: s_cselect_b32 s16, 1, 0
+; GFX6-NEXT: s_cselect_b32 s18, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s12, 0
-; GFX6-NEXT: s_cselect_b32 s17, 1, 0
-; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], s12
-; GFX6-NEXT: s_lshr_b64 s[14:15], s[0:1], s13
+; GFX6-NEXT: s_cselect_b32 s19, 1, 0
+; GFX6-NEXT: s_lshl_b64 s[14:15], s[0:1], s12
+; GFX6-NEXT: s_lshr_b64 s[16:17], s[0:1], s10
; GFX6-NEXT: s_lshl_b64 s[12:13], s[2:3], s12
-; GFX6-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13]
+; GFX6-NEXT: s_or_b64 s[12:13], s[16:17], s[12:13]
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
-; GFX6-NEXT: s_cmp_lg_u32 s16, 0
-; GFX6-NEXT: s_cselect_b64 s[10:11], s[10:11], 0
+; GFX6-NEXT: s_cmp_lg_u32 s18, 0
+; GFX6-NEXT: s_cselect_b64 s[14:15], s[14:15], 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1]
-; GFX6-NEXT: s_cmp_lg_u32 s17, 0
+; GFX6-NEXT: s_cmp_lg_u32 s19, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX6-NEXT: s_sub_i32 s9, 64, 1
; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
+; GFX6-NEXT: s_lshl_b32 s7, s6, 31
; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
-; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], s9
+; GFX6-NEXT: s_mov_b32 s6, s11
; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
-; GFX6-NEXT: s_sub_i32 s14, s8, 64
-; GFX6-NEXT: s_sub_i32 s12, 64, s8
+; GFX6-NEXT: s_sub_i32 s12, s8, 64
+; GFX6-NEXT: s_sub_i32 s10, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64
-; GFX6-NEXT: s_cselect_b32 s15, 1, 0
+; GFX6-NEXT: s_cselect_b32 s13, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b32 s16, 1, 0
; GFX6-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
-; GFX6-NEXT: s_lshl_b64 s[12:13], s[0:1], s12
+; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], s10
; GFX6-NEXT: s_lshr_b64 s[8:9], s[4:5], s8
-; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s14
-; GFX6-NEXT: s_cmp_lg_u32 s15, 0
+; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
+; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s12
+; GFX6-NEXT: s_cmp_lg_u32 s13, 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX6-NEXT: s_cmp_lg_u32 s16, 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1]
-; GFX6-NEXT: s_cmp_lg_u32 s15, 0
+; GFX6-NEXT: s_cmp_lg_u32 s13, 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[6:7], 0
-; GFX6-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1]
+; GFX6-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX6-NEXT: ; return to shader part epilog
;
@@ -4754,44 +4720,44 @@ define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
; GFX8-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX8-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX8-NEXT: s_sub_i32 s9, s12, 64
-; GFX8-NEXT: s_sub_i32 s13, 64, s12
+; GFX8-NEXT: s_sub_i32 s10, 64, s12
; GFX8-NEXT: s_cmp_lt_u32 s12, 64
-; GFX8-NEXT: s_cselect_b32 s16, 1, 0
+; GFX8-NEXT: s_cselect_b32 s18, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s12, 0
-; GFX8-NEXT: s_cselect_b32 s17, 1, 0
-; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], s12
-; GFX8-NEXT: s_lshr_b64 s[14:15], s[0:1], s13
+; GFX8-NEXT: s_cselect_b32 s19, 1, 0
+; GFX8-NEXT: s_lshl_b64 s[14:15], s[0:1], s12
+; GFX8-NEXT: s_lshr_b64 s[16:17], s[0:1], s10
; GFX8-NEXT: s_lshl_b64 s[12:13], s[2:3], s12
-; GFX8-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13]
+; GFX8-NEXT: s_or_b64 s[12:13], s[16:17], s[12:13]
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
-; GFX8-NEXT: s_cmp_lg_u32 s16, 0
-; GFX8-NEXT: s_cselect_b64 s[10:11], s[10:11], 0
+; GFX8-NEXT: s_cmp_lg_u32 s18, 0
+; GFX8-NEXT: s_cselect_b64 s[14:15], s[14:15], 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1]
-; GFX8-NEXT: s_cmp_lg_u32 s17, 0
+; GFX8-NEXT: s_cmp_lg_u32 s19, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX8-NEXT: s_sub_i32 s9, 64, 1
; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
+; GFX8-NEXT: s_lshl_b32 s7, s6, 31
; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
-; GFX8-NEXT: s_lshl_b64 s[6:7], s[6:7], s9
+; GFX8-NEXT: s_mov_b32 s6, s11
; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
-; GFX8-NEXT: s_sub_i32 s14, s8, 64
-; GFX8-NEXT: s_sub_i32 s12, 64, s8
+; GFX8-NEXT: s_sub_i32 s12, s8, 64
+; GFX8-NEXT: s_sub_i32 s10, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64
-; GFX8-NEXT: s_cselect_b32 s15, 1, 0
+; GFX8-NEXT: s_cselect_b32 s13, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b32 s16, 1, 0
; GFX8-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
-; GFX8-NEXT: s_lshl_b64 s[12:13], s[0:1], s12
+; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], s10
; GFX8-NEXT: s_lshr_b64 s[8:9], s[4:5], s8
-; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s14
-; GFX8-NEXT: s_cmp_lg_u32 s15, 0
+; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
+; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s12
+; GFX8-NEXT: s_cmp_lg_u32 s13, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX8-NEXT: s_cmp_lg_u32 s16, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1]
-; GFX8-NEXT: s_cmp_lg_u32 s15, 0
+; GFX8-NEXT: s_cmp_lg_u32 s13, 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[6:7], 0
-; GFX8-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1]
+; GFX8-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX8-NEXT: ; return to shader part epilog
;
@@ -4801,44 +4767,44 @@ define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
; GFX9-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX9-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX9-NEXT: s_sub_i32 s9, s12, 64
-; GFX9-NEXT: s_sub_i32 s13, 64, s12
+; GFX9-NEXT: s_sub_i32 s10, 64, s12
; GFX9-NEXT: s_cmp_lt_u32 s12, 64
-; GFX9-NEXT: s_cselect_b32 s16, 1, 0
+; GFX9-NEXT: s_cselect_b32 s18, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s12, 0
-; GFX9-NEXT: s_cselect_b32 s17, 1, 0
-; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], s12
-; GFX9-NEXT: s_lshr_b64 s[14:15], s[0:1], s13
+; GFX9-NEXT: s_cselect_b32 s19, 1, 0
+; GFX9-NEXT: s_lshl_b64 s[14:15], s[0:1], s12
+; GFX9-NEXT: s_lshr_b64 s[16:17], s[0:1], s10
; GFX9-NEXT: s_lshl_b64 s[12:13], s[2:3], s12
-; GFX9-NEXT: s_or_b64 s[12:13], s[14:15], s[12:13]
+; GFX9-NEXT: s_or_b64 s[12:13], s[16:17], s[12:13]
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
-; GFX9-NEXT: s_cmp_lg_u32 s16, 0
-; GFX9-NEXT: s_cselect_b64 s[10:11], s[10:11], 0
+; GFX9-NEXT: s_cmp_lg_u32 s18, 0
+; GFX9-NEXT: s_cselect_b64 s[14:15], s[14:15], 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1]
-; GFX9-NEXT: s_cmp_lg_u32 s17, 0
+; GFX9-NEXT: s_cmp_lg_u32 s19, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX9-NEXT: s_sub_i32 s9, 64, 1
; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
+; GFX9-NEXT: s_lshl_b32 s7, s6, 31
; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
-; GFX9-NEXT: s_lshl_b64 s[6:7], s[6:7], s9
+; GFX9-NEXT: s_mov_b32 s6, s11
; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
-; GFX9-NEXT: s_sub_i32 s14, s8, 64
-; GFX9-NEXT: s_sub_i32 s12, 64, s8
+; GFX9-NEXT: s_sub_i32 s12, s8, 64
+; GFX9-NEXT: s_sub_i32 s10, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64
-; GFX9-NEXT: s_cselect_b32 s15, 1, 0
+; GFX9-NEXT: s_cselect_b32 s13, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b32 s16, 1, 0
; GFX9-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
-; GFX9-NEXT: s_lshl_b64 s[12:13], s[0:1], s12
+; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], s10
; GFX9-NEXT: s_lshr_b64 s[8:9], s[4:5], s8
-; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s14
-; GFX9-NEXT: s_cmp_lg_u32 s15, 0
+; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s12
+; GFX9-NEXT: s_cmp_lg_u32 s13, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX9-NEXT: s_cmp_lg_u32 s16, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1]
-; GFX9-NEXT: s_cmp_lg_u32 s15, 0
+; GFX9-NEXT: s_cmp_lg_u32 s13, 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[6:7], 0
-; GFX9-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1]
+; GFX9-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX9-NEXT: ; return to shader part epilog
;
@@ -4850,22 +4816,22 @@ define amdgpu_ps i128 @s_fshl_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
; GFX10-NEXT: s_sub_i32 s9, s12, 64
; GFX10-NEXT: s_sub_i32 s10, 64, s12
; GFX10-NEXT: s_cmp_lt_u32 s12, 64
-; GFX10-NEXT: s_cselect_b32 s16, 1, 0
+; GFX10-NEXT: s_cselect_b32 s18, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s12, 0
-; GFX10-NEXT: s_cselect_b32 s17, 1, 0
-; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], s12
-; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s10
+; GFX10-NEXT: s_cselect_b32 s19, 1, 0
+; GFX10-NEXT: s_lshl_b64 s[16:17], s[2:3], s12
+; GFX10-NEXT: s_lshr_b64 s[14:15], s[0:1], s10
; GFX10-NEXT: s_lshl_b64 s[12:13], s[0:1], s12
-; GFX10-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
+; GFX10-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
-; GFX10-NEXT: s_cmp_lg_u32 s16, 0
+; GFX10-NEXT: s_cmp_lg_u32 s18, 0
; GFX10-NEXT: s_cselect_b64 s[12:13], s[12:13], 0
-; GFX10-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1]
-; GFX10-NEXT: s_cmp_lg_u32 s17, 0
+; GFX10-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1]
+; GFX10-NEXT: s_cmp_lg_u32 s19, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX10-NEXT: s_sub_i32 s9, 64, 1
; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
-; GFX10-NEXT: s_lshl_b64 s[4:5], s[6:7], s9
+; GFX10-NEXT: s_lshl_b32 s5, s6, 31
+; GFX10-NEXT: s_mov_b32 s4, s11
; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX10-NEXT: s_sub_i32 s14, s8, 64
@@ -4914,28 +4880,26 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v14
-; GFX6-NEXT: s_sub_i32 s4, 64, 1
; GFX6-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc
-; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], 1
-; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], s4
-; GFX6-NEXT: v_lshr_b64 v[4:5], v[6:7], 1
+; GFX6-NEXT: v_lshr_b64 v[2:3], v[4:5], 1
+; GFX6-NEXT: v_lshr_b64 v[0:1], v[6:7], 1
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 31, v6
+; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 64, v15
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX6-NEXT: v_lshr_b64 v[2:3], v[0:1], v15
-; GFX6-NEXT: v_lshl_b64 v[6:7], v[4:5], v6
; GFX6-NEXT: v_subrev_i32_e32 v14, vcc, 64, v15
-; GFX6-NEXT: v_or_b32_e32 v6, v2, v6
-; GFX6-NEXT: v_or_b32_e32 v7, v3, v7
-; GFX6-NEXT: v_lshr_b64 v[2:3], v[4:5], v14
+; GFX6-NEXT: v_lshr_b64 v[4:5], v[2:3], v15
+; GFX6-NEXT: v_lshl_b64 v[6:7], v[0:1], v6
+; GFX6-NEXT: v_lshr_b64 v[8:9], v[0:1], v15
+; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v14
+; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], v15
-; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
; GFX6-NEXT: v_or_b32_e32 v0, v10, v0
@@ -4965,28 +4929,26 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v14
-; GFX8-NEXT: s_sub_i32 s4, 64, 1
; GFX8-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc
-; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[4:5]
-; GFX8-NEXT: v_lshlrev_b64 v[2:3], s4, v[6:7]
-; GFX8-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7]
+; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[4:5]
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[6:7]
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 31, v6
+; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 64, v15
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], v15, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[6:7], v6, v[4:5]
; GFX8-NEXT: v_subrev_u32_e32 v14, vcc, 64, v15
-; GFX8-NEXT: v_or_b32_e32 v6, v2, v6
-; GFX8-NEXT: v_or_b32_e32 v7, v3, v7
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], v14, v[4:5]
+; GFX8-NEXT: v_lshrrev_b64 v[4:5], v15, v[2:3]
+; GFX8-NEXT: v_lshlrev_b64 v[6:7], v6, v[0:1]
+; GFX8-NEXT: v_lshrrev_b64 v[8:9], v15, v[0:1]
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], v14, v[0:1]
+; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], v15, v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
; GFX8-NEXT: v_or_b32_e32 v0, v10, v0
@@ -5016,28 +4978,26 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v14
-; GFX9-NEXT: s_sub_i32 s4, 64, 1
; GFX9-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc
-; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[4:5]
-; GFX9-NEXT: v_lshlrev_b64 v[2:3], s4, v[6:7]
-; GFX9-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7]
+; GFX9-NEXT: v_lshrrev_b64 v[2:3], 1, v[4:5]
+; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[6:7]
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 31, v6
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_sub_u32_e32 v6, 64, v15
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_lshrrev_b64 v[2:3], v15, v[0:1]
-; GFX9-NEXT: v_lshlrev_b64 v[6:7], v6, v[4:5]
; GFX9-NEXT: v_subrev_u32_e32 v14, 64, v15
-; GFX9-NEXT: v_or_b32_e32 v6, v2, v6
-; GFX9-NEXT: v_or_b32_e32 v7, v3, v7
-; GFX9-NEXT: v_lshrrev_b64 v[2:3], v14, v[4:5]
+; GFX9-NEXT: v_lshrrev_b64 v[4:5], v15, v[2:3]
+; GFX9-NEXT: v_lshlrev_b64 v[6:7], v6, v[0:1]
+; GFX9-NEXT: v_lshrrev_b64 v[8:9], v15, v[0:1]
+; GFX9-NEXT: v_lshrrev_b64 v[0:1], v14, v[0:1]
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v6
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
-; GFX9-NEXT: v_lshrrev_b64 v[8:9], v15, v[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v15
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
; GFX9-NEXT: v_or_b32_e32 v0, v10, v0
@@ -5051,51 +5011,49 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_movk_i32 s4, 0x7f
-; GFX10-NEXT: v_xor_b32_e32 v10, -1, v8
-; GFX10-NEXT: v_and_b32_e32 v18, s4, v8
-; GFX10-NEXT: s_sub_i32 s5, 64, 1
; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[8:9], s5, v[6:7]
-; GFX10-NEXT: v_and_b32_e32 v19, s4, v10
-; GFX10-NEXT: v_sub_nc_u32_e32 v11, 64, v18
-; GFX10-NEXT: v_lshlrev_b64 v[12:13], v18, v[2:3]
+; GFX10-NEXT: v_and_b32_e32 v18, s4, v8
+; GFX10-NEXT: v_xor_b32_e32 v8, -1, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v12, 31, v6
; GFX10-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
+; GFX10-NEXT: v_sub_nc_u32_e32 v9, 64, v18
+; GFX10-NEXT: v_and_b32_e32 v19, s4, v8
+; GFX10-NEXT: v_lshlrev_b64 v[10:11], v18, v[2:3]
+; GFX10-NEXT: v_or_b32_e32 v5, v5, v12
; GFX10-NEXT: v_subrev_nc_u32_e32 v20, 64, v18
+; GFX10-NEXT: v_lshrrev_b64 v[8:9], v9, v[0:1]
; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v19
-; GFX10-NEXT: v_lshrrev_b64 v[10:11], v11, v[0:1]
-; GFX10-NEXT: v_or_b32_e32 v4, v4, v8
-; GFX10-NEXT: v_or_b32_e32 v5, v5, v9
-; GFX10-NEXT: v_lshlrev_b64 v[8:9], v18, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7]
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v20, v[0:1]
-; GFX10-NEXT: v_or_b32_e32 v12, v10, v12
+; GFX10-NEXT: v_lshlrev_b64 v[12:13], v18, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[14:15], v19, v[4:5]
-; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v19
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], v20, v[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18
-; GFX10-NEXT: v_or_b32_e32 v13, v11, v13
+; GFX10-NEXT: v_or_b32_e32 v10, v8, v10
+; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7]
+; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v19
+; GFX10-NEXT: v_or_b32_e32 v11, v9, v11
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v19
-; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v19
-; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[6:7]
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v0, v10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v18
+; GFX10-NEXT: v_lshrrev_b64 v[8:9], v8, v[6:7]
; GFX10-NEXT: v_or_b32_e32 v14, v14, v16
; GFX10-NEXT: v_or_b32_e32 v15, v15, v17
-; GFX10-NEXT: v_cndmask_b32_e32 v12, v0, v12, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v13, v1, v13, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v1, v11, vcc_lo
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7]
-; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v18
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v14, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v11, v15, s4
-; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v12, v2, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v13, v3, s6
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v19
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v14, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v9, v15, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, v2, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s5
; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, v5, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, v4, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, v3, s6
+; GFX10-NEXT: v_or_b32_e32 v0, v12, v4
; GFX10-NEXT: v_or_b32_e32 v1, v7, v5
-; GFX10-NEXT: v_or_b32_e32 v3, v3, v9
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
-; GFX10-NEXT: v_or_b32_e32 v0, v8, v4
+; GFX10-NEXT: v_or_b32_e32 v3, v3, v8
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
ret i128 %result
@@ -5117,21 +5075,21 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX6-NEXT: v_or_b32_e32 v3, v1, v3
; GFX6-NEXT: v_lshl_b64 v[0:1], s[0:1], v8
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
-; GFX6-NEXT: s_sub_i32 s8, 64, 1
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: s_mov_b32 s8, 0
; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc
; GFX6-NEXT: v_mov_b32_e32 v2, s2
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX6-NEXT: v_mov_b32_e32 v3, s3
; GFX6-NEXT: s_lshr_b64 s[2:3], s[4:5], 1
-; GFX6-NEXT: s_lshl_b64 s[4:5], s[6:7], s8
+; GFX6-NEXT: s_lshl_b32 s9, s6, 31
; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
; GFX6-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v10, v1, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v7
-; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
+; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX6-NEXT: v_lshr_b64 v[0:1], s[2:3], v7
; GFX6-NEXT: v_lshl_b64 v[2:3], s[0:1], v2
; GFX6-NEXT: v_subrev_i32_e32 v11, vcc, 64, v7
@@ -5170,21 +5128,21 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX8-NEXT: v_or_b32_e32 v3, v1, v3
; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, s[0:1]
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
-; GFX8-NEXT: s_sub_i32 s8, 64, 1
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: s_mov_b32 s8, 0
; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: s_lshr_b64 s[2:3], s[4:5], 1
-; GFX8-NEXT: s_lshl_b64 s[4:5], s[6:7], s8
+; GFX8-NEXT: s_lshl_b32 s9, s6, 31
; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
; GFX8-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v10, v1, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 64, v7
-; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
+; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX8-NEXT: v_lshrrev_b64 v[0:1], v7, s[2:3]
; GFX8-NEXT: v_lshlrev_b64 v[2:3], v2, s[0:1]
; GFX8-NEXT: v_subrev_u32_e32 v11, vcc, 64, v7
@@ -5223,19 +5181,19 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX9-NEXT: v_or_b32_e32 v3, v1, v3
; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, s[0:1]
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6
-; GFX9-NEXT: s_sub_i32 s8, 64, 1
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: s_mov_b32 s8, 0
; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v5, vcc
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], 1
-; GFX9-NEXT: s_lshl_b64 s[4:5], s[6:7], s8
+; GFX9-NEXT: s_lshl_b32 s9, s6, 31
; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc
; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
-; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
+; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX9-NEXT: v_sub_u32_e32 v2, 64, v7
; GFX9-NEXT: v_cndmask_b32_e32 v10, v1, v3, vcc
; GFX9-NEXT: v_lshrrev_b64 v[0:1], v7, s[2:3]
@@ -5263,15 +5221,15 @@ define amdgpu_ps <4 x float> @v_fshl_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
;
; GFX10-LABEL: v_fshl_i128_ssv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_movk_i32 s8, 0x7f
+; GFX10-NEXT: s_movk_i32 s9, 0x7f
; GFX10-NEXT: v_xor_b32_e32 v4, -1, v0
-; GFX10-NEXT: v_and_b32_e32 v12, s8, v0
-; GFX10-NEXT: s_sub_i32 s9, 64, 1
+; GFX10-NEXT: v_and_b32_e32 v12, s9, v0
+; GFX10-NEXT: s_mov_b32 s8, 0
; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
-; GFX10-NEXT: v_and_b32_e32 v13, s8, v4
+; GFX10-NEXT: v_and_b32_e32 v13, s9, v4
; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v12
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v12, s[2:3]
-; GFX10-NEXT: s_lshl_b64 s[8:9], s[6:7], s9
+; GFX10-NEXT: s_lshl_b32 s9, s6, 31
; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
; GFX10-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v2, s[0:1]
@@ -5335,37 +5293,35 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX6-NEXT: s_cmp_lg_u32 s13, 0
-; GFX6-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
-; GFX6-NEXT: s_sub_i32 s2, 64, 1
-; GFX6-NEXT: v_lshl_b64 v[4:5], v[2:3], s2
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 1
-; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
+; GFX6-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
+; GFX6-NEXT: v_lshr_b64 v[3:4], v[2:3], 1
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 31, v2
; GFX6-NEXT: s_sub_i32 s3, 64, s4
; GFX6-NEXT: s_sub_i32 s2, s4, 64
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_cmp_lt_u32 s4, 64
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
; GFX6-NEXT: s_cselect_b32 s5, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s4, 0
-; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s4
-; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s3
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], s4
+; GFX6-NEXT: v_lshr_b64 v[5:6], v[0:1], s4
+; GFX6-NEXT: v_lshl_b64 v[7:8], v[3:4], s3
+; GFX6-NEXT: v_lshr_b64 v[9:10], v[3:4], s4
; GFX6-NEXT: s_cselect_b32 s8, 1, 0
-; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s2
+; GFX6-NEXT: v_lshr_b64 v[2:3], v[3:4], s2
; GFX6-NEXT: s_and_b32 s2, 1, s5
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
-; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX6-NEXT: v_or_b32_e32 v6, v6, v8
; GFX6-NEXT: s_and_b32 s2, 1, s8
-; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
; GFX6-NEXT: s_and_b32 s2, 1, s5
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
-; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v10, vcc
; GFX6-NEXT: v_or_b32_e32 v0, s6, v0
; GFX6-NEXT: v_or_b32_e32 v1, s7, v1
; GFX6-NEXT: v_or_b32_e32 v2, s0, v2
@@ -5392,37 +5348,35 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX8-NEXT: s_cmp_lg_u32 s13, 0
-; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
-; GFX8-NEXT: s_sub_i32 s2, 64, 1
-; GFX8-NEXT: v_lshlrev_b64 v[4:5], s2, v[2:3]
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
+; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
+; GFX8-NEXT: v_lshrrev_b64 v[3:4], 1, v[2:3]
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 31, v2
; GFX8-NEXT: s_sub_i32 s3, 64, s4
; GFX8-NEXT: s_sub_i32 s2, s4, 64
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: s_cmp_lt_u32 s4, 64
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v5
; GFX8-NEXT: s_cselect_b32 s5, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s4, 0
-; GFX8-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[6:7], s3, v[2:3]
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], s4, v[2:3]
+; GFX8-NEXT: v_lshrrev_b64 v[5:6], s4, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[7:8], s3, v[3:4]
+; GFX8-NEXT: v_lshrrev_b64 v[9:10], s4, v[3:4]
; GFX8-NEXT: s_cselect_b32 s8, 1, 0
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], s2, v[2:3]
+; GFX8-NEXT: v_lshrrev_b64 v[2:3], s2, v[3:4]
; GFX8-NEXT: s_and_b32 s2, 1, s5
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
-; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX8-NEXT: v_or_b32_e32 v6, v6, v8
; GFX8-NEXT: s_and_b32 s2, 1, s8
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
; GFX8-NEXT: s_and_b32 s2, 1, s5
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
-; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v10, vcc
; GFX8-NEXT: v_or_b32_e32 v0, s6, v0
; GFX8-NEXT: v_or_b32_e32 v1, s7, v1
; GFX8-NEXT: v_or_b32_e32 v2, s0, v2
@@ -5449,37 +5403,35 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX9-NEXT: s_cmp_lg_u32 s13, 0
-; GFX9-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
-; GFX9-NEXT: s_sub_i32 s2, 64, 1
-; GFX9-NEXT: v_lshlrev_b64 v[4:5], s2, v[2:3]
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
-; GFX9-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
+; GFX9-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
+; GFX9-NEXT: v_lshrrev_b64 v[3:4], 1, v[2:3]
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 31, v2
; GFX9-NEXT: s_sub_i32 s3, 64, s4
; GFX9-NEXT: s_sub_i32 s2, s4, 64
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: s_cmp_lt_u32 s4, 64
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v5
; GFX9-NEXT: s_cselect_b32 s5, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s4, 0
-; GFX9-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
-; GFX9-NEXT: v_lshlrev_b64 v[6:7], s3, v[2:3]
-; GFX9-NEXT: v_lshrrev_b64 v[8:9], s4, v[2:3]
+; GFX9-NEXT: v_lshrrev_b64 v[5:6], s4, v[0:1]
+; GFX9-NEXT: v_lshlrev_b64 v[7:8], s3, v[3:4]
+; GFX9-NEXT: v_lshrrev_b64 v[9:10], s4, v[3:4]
; GFX9-NEXT: s_cselect_b32 s8, 1, 0
-; GFX9-NEXT: v_lshrrev_b64 v[2:3], s2, v[2:3]
+; GFX9-NEXT: v_lshrrev_b64 v[2:3], s2, v[3:4]
; GFX9-NEXT: s_and_b32 s2, 1, s5
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v6
; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
; GFX9-NEXT: s_and_b32 s2, 1, s8
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
; GFX9-NEXT: s_and_b32 s2, 1, s5
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v10, vcc
; GFX9-NEXT: v_or_b32_e32 v0, s6, v0
; GFX9-NEXT: v_or_b32_e32 v1, s7, v1
; GFX9-NEXT: v_or_b32_e32 v2, s0, v2
@@ -5495,8 +5447,10 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX10-NEXT: s_sub_i32 s5, s8, 64
; GFX10-NEXT: s_sub_i32 s6, 64, s8
; GFX10-NEXT: s_cmp_lt_u32 s8, 64
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 31, v2
; GFX10-NEXT: s_cselect_b32 s12, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0
+; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: s_cselect_b32 s13, 1, 0
; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s8
; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s6
@@ -5504,29 +5458,25 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
; GFX10-NEXT: s_cmp_lg_u32 s12, 0
+; GFX10-NEXT: v_or_b32_e32 v1, v1, v4
; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX10-NEXT: s_sub_i32 s0, 64, 1
-; GFX10-NEXT: v_lshlrev_b64 v[4:5], s0, v[2:3]
-; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: s_sub_i32 s0, 64, s4
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX10-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3]
; GFX10-NEXT: s_sub_i32 s0, s4, 64
; GFX10-NEXT: s_cmp_lt_u32 s4, 64
; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3]
-; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s4, 0
-; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3]
-; GFX10-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX10-NEXT: s_cselect_b32 s0, 1, 0
+; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo
; GFX10-NEXT: s_and_b32 s0, 1, s0
+; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3]
; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
@@ -5554,39 +5504,39 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX6-NEXT: s_sub_i32 s6, 64, s8
; GFX6-NEXT: s_sub_i32 s5, s8, 64
; GFX6-NEXT: s_cmp_lt_u32 s8, 64
-; GFX6-NEXT: s_cselect_b32 s7, 1, 0
+; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0
+; GFX6-NEXT: s_cselect_b32 s10, 1, 0
; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s6
; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s8
-; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], s8
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s5
-; GFX6-NEXT: s_and_b32 s5, 1, s7
-; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
-; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
; GFX6-NEXT: s_and_b32 s5, 1, s9
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
-; GFX6-NEXT: s_sub_i32 s5, 64, 1
-; GFX6-NEXT: s_lshr_b64 s[6:7], s[2:3], 1
+; GFX6-NEXT: s_lshr_b64 s[8:9], s[2:3], 1
+; GFX6-NEXT: s_lshl_b32 s3, s2, 31
; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s5
+; GFX6-NEXT: s_mov_b32 s2, s7
+; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
+; GFX6-NEXT: s_and_b32 s5, 1, s10
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX6-NEXT: s_sub_i32 s10, s4, 64
-; GFX6-NEXT: s_sub_i32 s8, 64, s4
+; GFX6-NEXT: s_sub_i32 s6, 64, s4
; GFX6-NEXT: s_cmp_lt_u32 s4, 64
+; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
; GFX6-NEXT: s_cselect_b32 s11, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s4, 0
; GFX6-NEXT: s_cselect_b32 s12, 1, 0
-; GFX6-NEXT: s_lshr_b64 s[2:3], s[6:7], s4
-; GFX6-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
+; GFX6-NEXT: s_lshr_b64 s[2:3], s[8:9], s4
; GFX6-NEXT: s_lshr_b64 s[4:5], s[0:1], s4
-; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
-; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], s10
+; GFX6-NEXT: s_lshl_b64 s[6:7], s[8:9], s6
+; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
+; GFX6-NEXT: s_lshr_b64 s[6:7], s[8:9], s10
; GFX6-NEXT: s_cmp_lg_u32 s11, 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
; GFX6-NEXT: s_cmp_lg_u32 s12, 0
@@ -5609,39 +5559,39 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX8-NEXT: s_sub_i32 s6, 64, s8
; GFX8-NEXT: s_sub_i32 s5, s8, 64
; GFX8-NEXT: s_cmp_lt_u32 s8, 64
-; GFX8-NEXT: s_cselect_b32 s7, 1, 0
+; GFX8-NEXT: s_cselect_b32 s9, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0
+; GFX8-NEXT: s_cselect_b32 s10, 1, 0
; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3]
-; GFX8-NEXT: s_cselect_b32 s9, 1, 0
; GFX8-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
-; GFX8-NEXT: s_and_b32 s5, 1, s7
-; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
-; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
; GFX8-NEXT: s_and_b32 s5, 1, s9
-; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
-; GFX8-NEXT: s_sub_i32 s5, 64, 1
-; GFX8-NEXT: s_lshr_b64 s[6:7], s[2:3], 1
+; GFX8-NEXT: s_lshr_b64 s[8:9], s[2:3], 1
+; GFX8-NEXT: s_lshl_b32 s3, s2, 31
; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], s5
+; GFX8-NEXT: s_mov_b32 s2, s7
+; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
+; GFX8-NEXT: s_and_b32 s5, 1, s10
; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX8-NEXT: s_sub_i32 s10, s4, 64
-; GFX8-NEXT: s_sub_i32 s8, 64, s4
+; GFX8-NEXT: s_sub_i32 s6, 64, s4
; GFX8-NEXT: s_cmp_lt_u32 s4, 64
+; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
; GFX8-NEXT: s_cselect_b32 s11, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s4, 0
; GFX8-NEXT: s_cselect_b32 s12, 1, 0
-; GFX8-NEXT: s_lshr_b64 s[2:3], s[6:7], s4
-; GFX8-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
+; GFX8-NEXT: s_lshr_b64 s[2:3], s[8:9], s4
; GFX8-NEXT: s_lshr_b64 s[4:5], s[0:1], s4
-; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
-; GFX8-NEXT: s_lshr_b64 s[6:7], s[6:7], s10
+; GFX8-NEXT: s_lshl_b64 s[6:7], s[8:9], s6
+; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
+; GFX8-NEXT: s_lshr_b64 s[6:7], s[8:9], s10
; GFX8-NEXT: s_cmp_lg_u32 s11, 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
; GFX8-NEXT: s_cmp_lg_u32 s12, 0
@@ -5664,39 +5614,39 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX9-NEXT: s_sub_i32 s6, 64, s8
; GFX9-NEXT: s_sub_i32 s5, s8, 64
; GFX9-NEXT: s_cmp_lt_u32 s8, 64
-; GFX9-NEXT: s_cselect_b32 s7, 1, 0
+; GFX9-NEXT: s_cselect_b32 s9, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0
+; GFX9-NEXT: s_cselect_b32 s10, 1, 0
; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3]
-; GFX9-NEXT: s_cselect_b32 s9, 1, 0
; GFX9-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
-; GFX9-NEXT: s_and_b32 s5, 1, s7
-; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: s_and_b32 s5, 1, s9
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
-; GFX9-NEXT: s_sub_i32 s5, 64, 1
-; GFX9-NEXT: s_lshr_b64 s[6:7], s[2:3], 1
+; GFX9-NEXT: s_lshr_b64 s[8:9], s[2:3], 1
+; GFX9-NEXT: s_lshl_b32 s3, s2, 31
; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
-; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s5
+; GFX9-NEXT: s_mov_b32 s2, s7
+; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
+; GFX9-NEXT: s_and_b32 s5, 1, s10
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX9-NEXT: s_sub_i32 s10, s4, 64
-; GFX9-NEXT: s_sub_i32 s8, 64, s4
+; GFX9-NEXT: s_sub_i32 s6, 64, s4
; GFX9-NEXT: s_cmp_lt_u32 s4, 64
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: s_cselect_b32 s11, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s4, 0
; GFX9-NEXT: s_cselect_b32 s12, 1, 0
-; GFX9-NEXT: s_lshr_b64 s[2:3], s[6:7], s4
-; GFX9-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
+; GFX9-NEXT: s_lshr_b64 s[2:3], s[8:9], s4
; GFX9-NEXT: s_lshr_b64 s[4:5], s[0:1], s4
-; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
-; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], s10
+; GFX9-NEXT: s_lshl_b64 s[6:7], s[8:9], s6
+; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_lshr_b64 s[6:7], s[8:9], s10
; GFX9-NEXT: s_cmp_lg_u32 s11, 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
; GFX9-NEXT: s_cmp_lg_u32 s12, 0
@@ -5715,7 +5665,7 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
-; GFX10-NEXT: s_andn2_b64 s[6:7], s[6:7], s[4:5]
+; GFX10-NEXT: s_andn2_b64 s[10:11], s[6:7], s[4:5]
; GFX10-NEXT: s_sub_i32 s4, 64, s8
; GFX10-NEXT: s_sub_i32 s5, s8, 64
; GFX10-NEXT: s_cmp_lt_u32 s8, 64
@@ -5724,43 +5674,43 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1]
-; GFX10-NEXT: s_cselect_b32 s7, 1, 0
+; GFX10-NEXT: s_cselect_b32 s6, 1, 0
; GFX10-NEXT: s_and_b32 s4, 1, vcc_lo
; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7
; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4
+; GFX10-NEXT: s_lshl_b32 s5, s2, 31
; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
-; GFX10-NEXT: s_and_b32 s7, 1, s7
-; GFX10-NEXT: s_sub_i32 s10, s6, 64
-; GFX10-NEXT: s_sub_i32 s8, 64, s6
+; GFX10-NEXT: s_and_b32 s6, 1, s6
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v4, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v5, s4
-; GFX10-NEXT: s_sub_i32 s4, 64, 1
-; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo
-; GFX10-NEXT: s_lshl_b64 s[4:5], s[2:3], s4
-; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
+; GFX10-NEXT: s_mov_b32 s4, s7
+; GFX10-NEXT: s_sub_i32 s11, s10, 64
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
-; GFX10-NEXT: s_cmp_lt_u32 s6, 64
-; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
-; GFX10-NEXT: s_cselect_b32 s11, 1, 0
-; GFX10-NEXT: s_cmp_eq_u32 s6, 0
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s7
+; GFX10-NEXT: s_sub_i32 s7, 64, s10
+; GFX10-NEXT: s_cmp_lt_u32 s10, 64
+; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo
; GFX10-NEXT: s_cselect_b32 s12, 1, 0
-; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s6
-; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
-; GFX10-NEXT: s_lshr_b64 s[6:7], s[2:3], s6
-; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
-; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
-; GFX10-NEXT: s_cmp_lg_u32 s11, 0
+; GFX10-NEXT: s_cmp_eq_u32 s10, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
+; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6
+; GFX10-NEXT: s_cselect_b32 s13, 1, 0
+; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s10
+; GFX10-NEXT: s_lshl_b64 s[6:7], s[2:3], s7
+; GFX10-NEXT: s_lshr_b64 s[8:9], s[2:3], s10
+; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
+; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s11
+; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
-; GFX10-NEXT: s_cmp_lg_u32 s12, 0
+; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
-; GFX10-NEXT: s_cmp_lg_u32 s11, 0
+; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: v_or_b32_e32 v0, s0, v6
-; GFX10-NEXT: s_cselect_b64 s[2:3], s[6:7], 0
+; GFX10-NEXT: s_cselect_b64 s[2:3], s[8:9], 0
; GFX10-NEXT: v_or_b32_e32 v1, s1, v7
; GFX10-NEXT: v_or_b32_e32 v2, s2, v2
; GFX10-NEXT: v_or_b32_e32 v3, s3, v3
@@ -5773,56 +5723,48 @@ define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
define amdgpu_ps i128 @s_fshl_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-LABEL: s_fshl_i128_65:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_sub_i32 s2, 0x41, 64
-; GFX6-NEXT: s_sub_i32 s4, 64, 63
; GFX6-NEXT: s_mov_b32 s9, 0
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[0:1], s2
+; GFX6-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
; GFX6-NEXT: s_lshr_b32 s8, s7, 31
; GFX6-NEXT: s_lshr_b32 s0, s5, 31
; GFX6-NEXT: s_mov_b32 s1, s9
-; GFX6-NEXT: s_lshl_b64 s[4:5], s[6:7], s4
+; GFX6-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fshl_i128_65:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_sub_i32 s2, 0x41, 64
-; GFX8-NEXT: s_sub_i32 s4, 64, 63
; GFX8-NEXT: s_mov_b32 s9, 0
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[0:1], s2
+; GFX8-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
; GFX8-NEXT: s_lshr_b32 s8, s7, 31
; GFX8-NEXT: s_lshr_b32 s0, s5, 31
; GFX8-NEXT: s_mov_b32 s1, s9
-; GFX8-NEXT: s_lshl_b64 s[4:5], s[6:7], s4
+; GFX8-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fshl_i128_65:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sub_i32 s2, 0x41, 64
-; GFX9-NEXT: s_sub_i32 s4, 64, 63
; GFX9-NEXT: s_mov_b32 s9, 0
-; GFX9-NEXT: s_lshl_b64 s[2:3], s[0:1], s2
+; GFX9-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
; GFX9-NEXT: s_lshr_b32 s8, s7, 31
; GFX9-NEXT: s_lshr_b32 s0, s5, 31
; GFX9-NEXT: s_mov_b32 s1, s9
-; GFX9-NEXT: s_lshl_b64 s[4:5], s[6:7], s4
+; GFX9-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_fshl_i128_65:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_i32 s2, 0x41, 64
-; GFX10-NEXT: s_sub_i32 s4, 64, 63
; GFX10-NEXT: s_mov_b32 s9, 0
-; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], s2
+; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
; GFX10-NEXT: s_lshr_b32 s0, s5, 31
; GFX10-NEXT: s_lshr_b32 s8, s7, 31
; GFX10-NEXT: s_mov_b32 s1, s9
-; GFX10-NEXT: s_lshl_b64 s[4:5], s[6:7], s4
+; GFX10-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX10-NEXT: ; return to shader part epilog
@@ -5834,10 +5776,8 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
; GFX6-LABEL: v_fshl_i128_65:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_sub_i32 s4, 0x41, 64
-; GFX6-NEXT: v_lshl_b64 v[2:3], v[0:1], s4
-; GFX6-NEXT: s_sub_i32 s4, 64, 63
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[6:7], s4
+; GFX6-NEXT: v_lshl_b64 v[2:3], v[0:1], 1
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[6:7], 1
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v7
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 31, v5
; GFX6-NEXT: v_or_b32_e32 v0, v5, v0
@@ -5847,10 +5787,8 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
; GFX8-LABEL: v_fshl_i128_65:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_sub_i32 s4, 0x41, 64
-; GFX8-NEXT: v_lshlrev_b64 v[2:3], s4, v[0:1]
-; GFX8-NEXT: s_sub_i32 s4, 64, 63
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], s4, v[6:7]
+; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v7
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 31, v5
; GFX8-NEXT: v_or_b32_e32 v0, v5, v0
@@ -5860,10 +5798,8 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
; GFX9-LABEL: v_fshl_i128_65:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_sub_i32 s4, 0x41, 64
-; GFX9-NEXT: v_lshlrev_b64 v[2:3], s4, v[0:1]
-; GFX9-NEXT: s_sub_i32 s4, 64, 63
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], s4, v[6:7]
+; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 31, v5
; GFX9-NEXT: v_or_b32_e32 v0, v5, v0
@@ -5874,10 +5810,8 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: s_sub_i32 s4, 0x41, 64
-; GFX10-NEXT: s_sub_i32 s5, 64, 63
-; GFX10-NEXT: v_lshlrev_b64 v[2:3], s4, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[6:7]
+; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v5
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 31, v7
; GFX10-NEXT: v_or_b32_e32 v0, v4, v0
@@ -5909,27 +5843,27 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX6-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1]
; GFX6-NEXT: s_cmp_lg_u32 s29, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX6-NEXT: s_sub_i32 s26, 64, 1
; GFX6-NEXT: s_lshr_b64 s[0:1], s[10:11], 1
+; GFX6-NEXT: s_lshl_b32 s11, s10, 31
; GFX6-NEXT: s_lshr_b64 s[8:9], s[8:9], 1
-; GFX6-NEXT: s_lshl_b64 s[10:11], s[10:11], s26
+; GFX6-NEXT: s_mov_b32 s10, s19
; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
-; GFX6-NEXT: s_sub_i32 s27, s16, 64
+; GFX6-NEXT: s_sub_i32 s26, s16, 64
; GFX6-NEXT: s_sub_i32 s22, 64, s16
; GFX6-NEXT: s_cmp_lt_u32 s16, 64
-; GFX6-NEXT: s_cselect_b32 s28, 1, 0
+; GFX6-NEXT: s_cselect_b32 s27, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s16, 0
-; GFX6-NEXT: s_cselect_b32 s29, 1, 0
+; GFX6-NEXT: s_cselect_b32 s28, 1, 0
; GFX6-NEXT: s_lshr_b64 s[10:11], s[0:1], s16
; GFX6-NEXT: s_lshl_b64 s[22:23], s[0:1], s22
; GFX6-NEXT: s_lshr_b64 s[16:17], s[8:9], s16
; GFX6-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23]
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s27
-; GFX6-NEXT: s_cmp_lg_u32 s28, 0
+; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s26
+; GFX6-NEXT: s_cmp_lg_u32 s27, 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1]
-; GFX6-NEXT: s_cmp_lg_u32 s29, 0
-; GFX6-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX6-NEXT: s_cmp_lg_u32 s28, 0
+; GFX6-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
+; GFX6-NEXT: s_cmp_lg_u32 s27, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX6-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
@@ -5938,21 +5872,22 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX6-NEXT: s_sub_i32 s11, s8, 64
; GFX6-NEXT: s_sub_i32 s9, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64
-; GFX6-NEXT: s_cselect_b32 s20, 1, 0
+; GFX6-NEXT: s_cselect_b32 s18, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0
-; GFX6-NEXT: s_cselect_b32 s21, 1, 0
+; GFX6-NEXT: s_cselect_b32 s22, 1, 0
; GFX6-NEXT: s_lshl_b64 s[16:17], s[4:5], s8
-; GFX6-NEXT: s_lshr_b64 s[18:19], s[4:5], s9
+; GFX6-NEXT: s_lshr_b64 s[20:21], s[4:5], s9
; GFX6-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
-; GFX6-NEXT: s_or_b64 s[8:9], s[18:19], s[8:9]
+; GFX6-NEXT: s_or_b64 s[8:9], s[20:21], s[8:9]
; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], s11
-; GFX6-NEXT: s_cmp_lg_u32 s20, 0
+; GFX6-NEXT: s_cmp_lg_u32 s18, 0
; GFX6-NEXT: s_cselect_b64 s[16:17], s[16:17], 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
-; GFX6-NEXT: s_cmp_lg_u32 s21, 0
+; GFX6-NEXT: s_cmp_lg_u32 s22, 0
; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX6-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
-; GFX6-NEXT: s_lshl_b64 s[12:13], s[14:15], s26
+; GFX6-NEXT: s_lshl_b32 s13, s14, 31
+; GFX6-NEXT: s_mov_b32 s12, s19
; GFX6-NEXT: s_lshr_b64 s[4:5], s[14:15], 1
; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
; GFX6-NEXT: s_sub_i32 s18, s10, 64
@@ -5997,27 +5932,27 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX8-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1]
; GFX8-NEXT: s_cmp_lg_u32 s29, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX8-NEXT: s_sub_i32 s26, 64, 1
; GFX8-NEXT: s_lshr_b64 s[0:1], s[10:11], 1
+; GFX8-NEXT: s_lshl_b32 s11, s10, 31
; GFX8-NEXT: s_lshr_b64 s[8:9], s[8:9], 1
-; GFX8-NEXT: s_lshl_b64 s[10:11], s[10:11], s26
+; GFX8-NEXT: s_mov_b32 s10, s19
; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
-; GFX8-NEXT: s_sub_i32 s27, s16, 64
+; GFX8-NEXT: s_sub_i32 s26, s16, 64
; GFX8-NEXT: s_sub_i32 s22, 64, s16
; GFX8-NEXT: s_cmp_lt_u32 s16, 64
-; GFX8-NEXT: s_cselect_b32 s28, 1, 0
+; GFX8-NEXT: s_cselect_b32 s27, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s16, 0
-; GFX8-NEXT: s_cselect_b32 s29, 1, 0
+; GFX8-NEXT: s_cselect_b32 s28, 1, 0
; GFX8-NEXT: s_lshr_b64 s[10:11], s[0:1], s16
; GFX8-NEXT: s_lshl_b64 s[22:23], s[0:1], s22
; GFX8-NEXT: s_lshr_b64 s[16:17], s[8:9], s16
; GFX8-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23]
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s27
-; GFX8-NEXT: s_cmp_lg_u32 s28, 0
+; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s26
+; GFX8-NEXT: s_cmp_lg_u32 s27, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1]
-; GFX8-NEXT: s_cmp_lg_u32 s29, 0
-; GFX8-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX8-NEXT: s_cmp_lg_u32 s28, 0
+; GFX8-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
+; GFX8-NEXT: s_cmp_lg_u32 s27, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX8-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
@@ -6026,21 +5961,22 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX8-NEXT: s_sub_i32 s11, s8, 64
; GFX8-NEXT: s_sub_i32 s9, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64
-; GFX8-NEXT: s_cselect_b32 s20, 1, 0
+; GFX8-NEXT: s_cselect_b32 s18, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0
-; GFX8-NEXT: s_cselect_b32 s21, 1, 0
+; GFX8-NEXT: s_cselect_b32 s22, 1, 0
; GFX8-NEXT: s_lshl_b64 s[16:17], s[4:5], s8
-; GFX8-NEXT: s_lshr_b64 s[18:19], s[4:5], s9
+; GFX8-NEXT: s_lshr_b64 s[20:21], s[4:5], s9
; GFX8-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
-; GFX8-NEXT: s_or_b64 s[8:9], s[18:19], s[8:9]
+; GFX8-NEXT: s_or_b64 s[8:9], s[20:21], s[8:9]
; GFX8-NEXT: s_lshl_b64 s[4:5], s[4:5], s11
-; GFX8-NEXT: s_cmp_lg_u32 s20, 0
+; GFX8-NEXT: s_cmp_lg_u32 s18, 0
; GFX8-NEXT: s_cselect_b64 s[16:17], s[16:17], 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
-; GFX8-NEXT: s_cmp_lg_u32 s21, 0
+; GFX8-NEXT: s_cmp_lg_u32 s22, 0
; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX8-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
-; GFX8-NEXT: s_lshl_b64 s[12:13], s[14:15], s26
+; GFX8-NEXT: s_lshl_b32 s13, s14, 31
+; GFX8-NEXT: s_mov_b32 s12, s19
; GFX8-NEXT: s_lshr_b64 s[4:5], s[14:15], 1
; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
; GFX8-NEXT: s_sub_i32 s18, s10, 64
@@ -6085,27 +6021,27 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX9-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1]
; GFX9-NEXT: s_cmp_lg_u32 s29, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX9-NEXT: s_sub_i32 s26, 64, 1
; GFX9-NEXT: s_lshr_b64 s[0:1], s[10:11], 1
+; GFX9-NEXT: s_lshl_b32 s11, s10, 31
; GFX9-NEXT: s_lshr_b64 s[8:9], s[8:9], 1
-; GFX9-NEXT: s_lshl_b64 s[10:11], s[10:11], s26
+; GFX9-NEXT: s_mov_b32 s10, s19
; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
-; GFX9-NEXT: s_sub_i32 s27, s16, 64
+; GFX9-NEXT: s_sub_i32 s26, s16, 64
; GFX9-NEXT: s_sub_i32 s22, 64, s16
; GFX9-NEXT: s_cmp_lt_u32 s16, 64
-; GFX9-NEXT: s_cselect_b32 s28, 1, 0
+; GFX9-NEXT: s_cselect_b32 s27, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s16, 0
-; GFX9-NEXT: s_cselect_b32 s29, 1, 0
+; GFX9-NEXT: s_cselect_b32 s28, 1, 0
; GFX9-NEXT: s_lshr_b64 s[10:11], s[0:1], s16
; GFX9-NEXT: s_lshl_b64 s[22:23], s[0:1], s22
; GFX9-NEXT: s_lshr_b64 s[16:17], s[8:9], s16
; GFX9-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23]
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s27
-; GFX9-NEXT: s_cmp_lg_u32 s28, 0
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s26
+; GFX9-NEXT: s_cmp_lg_u32 s27, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1]
-; GFX9-NEXT: s_cmp_lg_u32 s29, 0
-; GFX9-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
+; GFX9-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
+; GFX9-NEXT: s_cmp_lg_u32 s27, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX9-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
@@ -6114,21 +6050,22 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX9-NEXT: s_sub_i32 s11, s8, 64
; GFX9-NEXT: s_sub_i32 s9, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64
-; GFX9-NEXT: s_cselect_b32 s20, 1, 0
+; GFX9-NEXT: s_cselect_b32 s18, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0
-; GFX9-NEXT: s_cselect_b32 s21, 1, 0
+; GFX9-NEXT: s_cselect_b32 s22, 1, 0
; GFX9-NEXT: s_lshl_b64 s[16:17], s[4:5], s8
-; GFX9-NEXT: s_lshr_b64 s[18:19], s[4:5], s9
+; GFX9-NEXT: s_lshr_b64 s[20:21], s[4:5], s9
; GFX9-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
-; GFX9-NEXT: s_or_b64 s[8:9], s[18:19], s[8:9]
+; GFX9-NEXT: s_or_b64 s[8:9], s[20:21], s[8:9]
; GFX9-NEXT: s_lshl_b64 s[4:5], s[4:5], s11
-; GFX9-NEXT: s_cmp_lg_u32 s20, 0
+; GFX9-NEXT: s_cmp_lg_u32 s18, 0
; GFX9-NEXT: s_cselect_b64 s[16:17], s[16:17], 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
-; GFX9-NEXT: s_cmp_lg_u32 s21, 0
+; GFX9-NEXT: s_cmp_lg_u32 s22, 0
; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
-; GFX9-NEXT: s_lshl_b64 s[12:13], s[14:15], s26
+; GFX9-NEXT: s_lshl_b32 s13, s14, 31
+; GFX9-NEXT: s_mov_b32 s12, s19
; GFX9-NEXT: s_lshr_b64 s[4:5], s[14:15], 1
; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT: s_sub_i32 s18, s10, 64
@@ -6173,27 +6110,27 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX10-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s29, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
-; GFX10-NEXT: s_sub_i32 s26, 64, 1
; GFX10-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
-; GFX10-NEXT: s_lshl_b64 s[8:9], s[10:11], s26
+; GFX10-NEXT: s_lshl_b32 s9, s10, 31
+; GFX10-NEXT: s_mov_b32 s8, s19
; GFX10-NEXT: s_lshr_b64 s[10:11], s[10:11], 1
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
-; GFX10-NEXT: s_sub_i32 s27, s16, 64
+; GFX10-NEXT: s_sub_i32 s26, s16, 64
; GFX10-NEXT: s_sub_i32 s17, 64, s16
; GFX10-NEXT: s_cmp_lt_u32 s16, 64
-; GFX10-NEXT: s_cselect_b32 s28, 1, 0
+; GFX10-NEXT: s_cselect_b32 s27, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s16, 0
-; GFX10-NEXT: s_cselect_b32 s29, 1, 0
+; GFX10-NEXT: s_cselect_b32 s28, 1, 0
; GFX10-NEXT: s_lshr_b64 s[8:9], s[0:1], s16
; GFX10-NEXT: s_lshl_b64 s[24:25], s[10:11], s17
; GFX10-NEXT: s_lshr_b64 s[16:17], s[10:11], s16
; GFX10-NEXT: s_or_b64 s[8:9], s[8:9], s[24:25]
-; GFX10-NEXT: s_lshr_b64 s[10:11], s[10:11], s27
-; GFX10-NEXT: s_cmp_lg_u32 s28, 0
+; GFX10-NEXT: s_lshr_b64 s[10:11], s[10:11], s26
+; GFX10-NEXT: s_cmp_lg_u32 s27, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
-; GFX10-NEXT: s_cmp_lg_u32 s29, 0
-; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX10-NEXT: s_cmp_lg_u32 s28, 0
+; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
+; GFX10-NEXT: s_cmp_lg_u32 s27, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
; GFX10-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
@@ -6202,21 +6139,22 @@ define amdgpu_ps <2 x i128> @s_fshl_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX10-NEXT: s_sub_i32 s11, s8, 64
; GFX10-NEXT: s_sub_i32 s9, 64, s8
; GFX10-NEXT: s_cmp_lt_u32 s8, 64
-; GFX10-NEXT: s_cselect_b32 s20, 1, 0
+; GFX10-NEXT: s_cselect_b32 s18, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0
-; GFX10-NEXT: s_cselect_b32 s21, 1, 0
+; GFX10-NEXT: s_cselect_b32 s22, 1, 0
; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s9
-; GFX10-NEXT: s_lshl_b64 s[18:19], s[6:7], s8
+; GFX10-NEXT: s_lshl_b64 s[20:21], s[6:7], s8
; GFX10-NEXT: s_lshl_b64 s[8:9], s[4:5], s8
-; GFX10-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
+; GFX10-NEXT: s_or_b64 s[16:17], s[16:17], s[20:21]
; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], s11
-; GFX10-NEXT: s_cmp_lg_u32 s20, 0
+; GFX10-NEXT: s_cmp_lg_u32 s18, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5]
-; GFX10-NEXT: s_cmp_lg_u32 s21, 0
+; GFX10-NEXT: s_cmp_lg_u32 s22, 0
; GFX10-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX10-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
-; GFX10-NEXT: s_lshl_b64 s[12:13], s[14:15], s26
+; GFX10-NEXT: s_lshl_b32 s13, s14, 31
+; GFX10-NEXT: s_mov_b32 s12, s19
; GFX10-NEXT: s_lshr_b64 s[14:15], s[14:15], 1
; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13]
; GFX10-NEXT: s_sub_i32 s18, s10, 64
@@ -6247,21 +6185,19 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX6-LABEL: v_fshl_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_sub_i32 s6, 64, 1
-; GFX6-NEXT: v_lshl_b64 v[17:18], v[10:11], s6
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[8:9], 1
-; GFX6-NEXT: s_movk_i32 s7, 0x7f
-; GFX6-NEXT: v_and_b32_e32 v23, s7, v16
-; GFX6-NEXT: v_or_b32_e32 v8, v8, v17
-; GFX6-NEXT: v_xor_b32_e32 v16, -1, v16
+; GFX6-NEXT: s_movk_i32 s6, 0x7f
+; GFX6-NEXT: v_and_b32_e32 v23, s6, v16
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, 64, v23
-; GFX6-NEXT: v_and_b32_e32 v24, s7, v16
-; GFX6-NEXT: v_or_b32_e32 v9, v9, v18
; GFX6-NEXT: v_lshr_b64 v[17:18], v[0:1], v17
; GFX6-NEXT: v_lshl_b64 v[21:22], v[2:3], v23
+; GFX6-NEXT: v_xor_b32_e32 v16, -1, v16
+; GFX6-NEXT: v_lshr_b64 v[8:9], v[8:9], 1
+; GFX6-NEXT: v_and_b32_e32 v24, s6, v16
+; GFX6-NEXT: v_or_b32_e32 v21, v17, v21
+; GFX6-NEXT: v_lshlrev_b32_e32 v17, 31, v10
; GFX6-NEXT: v_lshr_b64 v[10:11], v[10:11], 1
+; GFX6-NEXT: v_or_b32_e32 v9, v9, v17
; GFX6-NEXT: v_sub_i32_e32 v16, vcc, 64, v24
-; GFX6-NEXT: v_or_b32_e32 v21, v17, v21
; GFX6-NEXT: v_or_b32_e32 v22, v18, v22
; GFX6-NEXT: v_lshl_b64 v[16:17], v[10:11], v16
; GFX6-NEXT: v_lshr_b64 v[18:19], v[8:9], v24
@@ -6293,9 +6229,9 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX6-NEXT: v_or_b32_e32 v1, v18, v3
; GFX6-NEXT: v_or_b32_e32 v2, v17, v8
; GFX6-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX6-NEXT: v_and_b32_e32 v16, s7, v20
+; GFX6-NEXT: v_and_b32_e32 v16, s6, v20
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v20
-; GFX6-NEXT: v_and_b32_e32 v17, s7, v8
+; GFX6-NEXT: v_and_b32_e32 v17, s6, v8
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v16
; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], v8
; GFX6-NEXT: v_lshl_b64 v[10:11], v[6:7], v16
@@ -6312,27 +6248,26 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
; GFX6-NEXT: v_cndmask_b32_e32 v16, v4, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v20, v5, v7, vcc
-; GFX6-NEXT: v_lshr_b64 v[4:5], v[12:13], 1
-; GFX6-NEXT: v_lshl_b64 v[6:7], v[14:15], s6
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[14:15], 1
+; GFX6-NEXT: v_lshr_b64 v[6:7], v[12:13], 1
+; GFX6-NEXT: v_lshlrev_b32_e32 v8, 31, v14
+; GFX6-NEXT: v_lshr_b64 v[4:5], v[14:15], 1
+; GFX6-NEXT: v_or_b32_e32 v7, v7, v8
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 64, v17
-; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX6-NEXT: v_lshr_b64 v[6:7], v[4:5], v17
-; GFX6-NEXT: v_lshl_b64 v[10:11], v[8:9], v10
+; GFX6-NEXT: v_lshr_b64 v[8:9], v[6:7], v17
+; GFX6-NEXT: v_lshl_b64 v[10:11], v[4:5], v10
; GFX6-NEXT: v_subrev_i32_e32 v12, vcc, 64, v17
-; GFX6-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX6-NEXT: v_or_b32_e32 v11, v7, v11
-; GFX6-NEXT: v_lshr_b64 v[6:7], v[8:9], v17
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[8:9], v12
+; GFX6-NEXT: v_or_b32_e32 v10, v8, v10
+; GFX6-NEXT: v_or_b32_e32 v11, v9, v11
+; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], v17
+; GFX6-NEXT: v_lshr_b64 v[4:5], v[4:5], v12
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17
-; GFX6-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v17
-; GFX6-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
-; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
; GFX6-NEXT: v_or_b32_e32 v4, v18, v4
; GFX6-NEXT: v_or_b32_e32 v5, v19, v5
; GFX6-NEXT: v_or_b32_e32 v6, v16, v6
@@ -6342,21 +6277,19 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX8-LABEL: v_fshl_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_sub_i32 s6, 64, 1
-; GFX8-NEXT: v_lshlrev_b64 v[17:18], s6, v[10:11]
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
-; GFX8-NEXT: s_movk_i32 s7, 0x7f
-; GFX8-NEXT: v_and_b32_e32 v23, s7, v16
-; GFX8-NEXT: v_or_b32_e32 v8, v8, v17
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v16
+; GFX8-NEXT: s_movk_i32 s6, 0x7f
+; GFX8-NEXT: v_and_b32_e32 v23, s6, v16
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, 64, v23
-; GFX8-NEXT: v_and_b32_e32 v24, s7, v16
-; GFX8-NEXT: v_or_b32_e32 v9, v9, v18
; GFX8-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
+; GFX8-NEXT: v_xor_b32_e32 v16, -1, v16
+; GFX8-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
+; GFX8-NEXT: v_and_b32_e32 v24, s6, v16
+; GFX8-NEXT: v_or_b32_e32 v21, v17, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 31, v10
; GFX8-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
+; GFX8-NEXT: v_or_b32_e32 v9, v9, v17
; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v24
-; GFX8-NEXT: v_or_b32_e32 v21, v17, v21
; GFX8-NEXT: v_or_b32_e32 v22, v18, v22
; GFX8-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11]
; GFX8-NEXT: v_lshrrev_b64 v[18:19], v24, v[8:9]
@@ -6388,9 +6321,9 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX8-NEXT: v_or_b32_e32 v1, v18, v3
; GFX8-NEXT: v_or_b32_e32 v2, v17, v8
; GFX8-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX8-NEXT: v_and_b32_e32 v16, s7, v20
+; GFX8-NEXT: v_and_b32_e32 v16, s6, v20
; GFX8-NEXT: v_xor_b32_e32 v8, -1, v20
-; GFX8-NEXT: v_and_b32_e32 v17, s7, v8
+; GFX8-NEXT: v_and_b32_e32 v17, s6, v8
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v16
; GFX8-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5]
; GFX8-NEXT: v_lshlrev_b64 v[10:11], v16, v[6:7]
@@ -6407,27 +6340,26 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
; GFX8-NEXT: v_cndmask_b32_e32 v16, v4, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v20, v5, v7, vcc
-; GFX8-NEXT: v_lshrrev_b64 v[4:5], 1, v[12:13]
-; GFX8-NEXT: v_lshlrev_b64 v[6:7], s6, v[14:15]
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], 1, v[14:15]
+; GFX8-NEXT: v_lshrrev_b64 v[6:7], 1, v[12:13]
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 31, v14
+; GFX8-NEXT: v_lshrrev_b64 v[4:5], 1, v[14:15]
+; GFX8-NEXT: v_or_b32_e32 v7, v7, v8
; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 64, v17
-; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX8-NEXT: v_lshrrev_b64 v[6:7], v17, v[4:5]
-; GFX8-NEXT: v_lshlrev_b64 v[10:11], v10, v[8:9]
+; GFX8-NEXT: v_lshrrev_b64 v[8:9], v17, v[6:7]
+; GFX8-NEXT: v_lshlrev_b64 v[10:11], v10, v[4:5]
; GFX8-NEXT: v_subrev_u32_e32 v12, vcc, 64, v17
-; GFX8-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX8-NEXT: v_or_b32_e32 v11, v7, v11
-; GFX8-NEXT: v_lshrrev_b64 v[6:7], v17, v[8:9]
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], v12, v[8:9]
+; GFX8-NEXT: v_or_b32_e32 v10, v8, v10
+; GFX8-NEXT: v_or_b32_e32 v11, v9, v11
+; GFX8-NEXT: v_lshrrev_b64 v[8:9], v17, v[4:5]
+; GFX8-NEXT: v_lshrrev_b64 v[4:5], v12, v[4:5]
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v17
-; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
; GFX8-NEXT: v_or_b32_e32 v4, v18, v4
; GFX8-NEXT: v_or_b32_e32 v5, v19, v5
; GFX8-NEXT: v_or_b32_e32 v6, v16, v6
@@ -6437,21 +6369,19 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX9-LABEL: v_fshl_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_sub_i32 s6, 64, 1
-; GFX9-NEXT: v_lshlrev_b64 v[17:18], s6, v[10:11]
-; GFX9-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
-; GFX9-NEXT: s_movk_i32 s7, 0x7f
-; GFX9-NEXT: v_and_b32_e32 v23, s7, v16
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v17
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v16
+; GFX9-NEXT: s_movk_i32 s6, 0x7f
+; GFX9-NEXT: v_and_b32_e32 v23, s6, v16
; GFX9-NEXT: v_sub_u32_e32 v17, 64, v23
-; GFX9-NEXT: v_and_b32_e32 v24, s7, v16
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v18
; GFX9-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
+; GFX9-NEXT: v_xor_b32_e32 v16, -1, v16
+; GFX9-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
+; GFX9-NEXT: v_and_b32_e32 v24, s6, v16
+; GFX9-NEXT: v_or_b32_e32 v21, v17, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 31, v10
; GFX9-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v17
; GFX9-NEXT: v_sub_u32_e32 v16, 64, v24
-; GFX9-NEXT: v_or_b32_e32 v21, v17, v21
; GFX9-NEXT: v_or_b32_e32 v22, v18, v22
; GFX9-NEXT: v_lshlrev_b64 v[16:17], v16, v[10:11]
; GFX9-NEXT: v_lshrrev_b64 v[18:19], v24, v[8:9]
@@ -6483,9 +6413,9 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX9-NEXT: v_or_b32_e32 v1, v18, v3
; GFX9-NEXT: v_or_b32_e32 v2, v17, v8
; GFX9-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX9-NEXT: v_and_b32_e32 v16, s7, v20
+; GFX9-NEXT: v_and_b32_e32 v16, s6, v20
; GFX9-NEXT: v_xor_b32_e32 v8, -1, v20
-; GFX9-NEXT: v_and_b32_e32 v17, s7, v8
+; GFX9-NEXT: v_and_b32_e32 v17, s6, v8
; GFX9-NEXT: v_sub_u32_e32 v8, 64, v16
; GFX9-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5]
; GFX9-NEXT: v_lshlrev_b64 v[10:11], v16, v[6:7]
@@ -6495,34 +6425,33 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX9-NEXT: v_lshlrev_b64 v[8:9], v16, v[4:5]
; GFX9-NEXT: v_lshlrev_b64 v[4:5], v18, v[4:5]
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v19, 0, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
; GFX9-NEXT: v_cndmask_b32_e32 v16, v4, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v20, v5, v7, vcc
-; GFX9-NEXT: v_lshrrev_b64 v[4:5], 1, v[12:13]
-; GFX9-NEXT: v_lshlrev_b64 v[6:7], s6, v[14:15]
-; GFX9-NEXT: v_lshrrev_b64 v[8:9], 1, v[14:15]
+; GFX9-NEXT: v_lshrrev_b64 v[6:7], 1, v[12:13]
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 31, v14
+; GFX9-NEXT: v_lshrrev_b64 v[4:5], 1, v[14:15]
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: v_sub_u32_e32 v10, 64, v17
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX9-NEXT: v_lshrrev_b64 v[6:7], v17, v[4:5]
-; GFX9-NEXT: v_lshlrev_b64 v[10:11], v10, v[8:9]
+; GFX9-NEXT: v_lshrrev_b64 v[8:9], v17, v[6:7]
+; GFX9-NEXT: v_lshlrev_b64 v[10:11], v10, v[4:5]
; GFX9-NEXT: v_subrev_u32_e32 v12, 64, v17
-; GFX9-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX9-NEXT: v_or_b32_e32 v11, v7, v11
-; GFX9-NEXT: v_lshrrev_b64 v[6:7], v17, v[8:9]
-; GFX9-NEXT: v_lshrrev_b64 v[8:9], v12, v[8:9]
+; GFX9-NEXT: v_or_b32_e32 v10, v8, v10
+; GFX9-NEXT: v_or_b32_e32 v11, v9, v11
+; GFX9-NEXT: v_lshrrev_b64 v[8:9], v17, v[4:5]
+; GFX9-NEXT: v_lshrrev_b64 v[4:5], v12, v[4:5]
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v17
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
; GFX9-NEXT: v_or_b32_e32 v4, v18, v4
; GFX9-NEXT: v_or_b32_e32 v5, v19, v5
; GFX9-NEXT: v_or_b32_e32 v6, v16, v6
@@ -6534,94 +6463,91 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_movk_i32 s7, 0x7f
-; GFX10-NEXT: v_xor_b32_e32 v18, -1, v16
-; GFX10-NEXT: v_and_b32_e32 v27, s7, v16
-; GFX10-NEXT: s_sub_i32 s8, 64, 1
; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[8:9]
-; GFX10-NEXT: v_lshlrev_b64 v[16:17], s8, v[10:11]
-; GFX10-NEXT: v_and_b32_e32 v28, s7, v18
-; GFX10-NEXT: v_sub_nc_u32_e32 v19, 64, v27
-; GFX10-NEXT: v_lshlrev_b64 v[21:22], v27, v[2:3]
+; GFX10-NEXT: v_and_b32_e32 v27, s7, v16
+; GFX10-NEXT: v_xor_b32_e32 v16, -1, v16
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 31, v10
; GFX10-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
+; GFX10-NEXT: v_sub_nc_u32_e32 v17, 64, v27
+; GFX10-NEXT: v_and_b32_e32 v28, s7, v16
+; GFX10-NEXT: v_lshlrev_b64 v[18:19], v27, v[2:3]
+; GFX10-NEXT: v_or_b32_e32 v9, v9, v21
; GFX10-NEXT: v_subrev_nc_u32_e32 v29, 64, v27
+; GFX10-NEXT: v_lshrrev_b64 v[16:17], v17, v[0:1]
; GFX10-NEXT: v_sub_nc_u32_e32 v25, 64, v28
-; GFX10-NEXT: v_lshrrev_b64 v[18:19], v19, v[0:1]
-; GFX10-NEXT: v_or_b32_e32 v8, v8, v16
-; GFX10-NEXT: v_or_b32_e32 v9, v9, v17
-; GFX10-NEXT: v_lshlrev_b64 v[16:17], v27, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[25:26], v25, v[10:11]
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v29, v[0:1]
-; GFX10-NEXT: v_or_b32_e32 v21, v18, v21
+; GFX10-NEXT: v_lshlrev_b64 v[21:22], v27, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[23:24], v28, v[8:9]
-; GFX10-NEXT: v_subrev_nc_u32_e32 v18, 64, v28
-; GFX10-NEXT: v_or_b32_e32 v22, v19, v22
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], v29, v[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v27
+; GFX10-NEXT: v_or_b32_e32 v18, v16, v18
+; GFX10-NEXT: v_lshlrev_b64 v[25:26], v25, v[10:11]
+; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 64, v28
+; GFX10-NEXT: v_or_b32_e32 v19, v17, v19
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v28
-; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v28
-; GFX10-NEXT: v_lshrrev_b64 v[18:19], v18, v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v18, v0, v18, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v27
+; GFX10-NEXT: v_lshrrev_b64 v[16:17], v16, v[10:11]
; GFX10-NEXT: v_or_b32_e32 v23, v23, v25
; GFX10-NEXT: v_or_b32_e32 v24, v24, v26
-; GFX10-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v27
-; GFX10-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v23, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v19, v1, v19, vcc_lo
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v28, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v19, v24, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v22, v3, s6
-; GFX10-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v18, v8, s5
-; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v28
+; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v23, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v17, v24, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v22, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v22, v19, v3, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v21, 0, v21, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v16, v8, s5
; GFX10-NEXT: v_cndmask_b32_e64 v8, v10, v9, s5
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v21, v2, s6
-; GFX10-NEXT: v_and_b32_e32 v24, s7, v20
-; GFX10-NEXT: v_or_b32_e32 v0, v16, v3
-; GFX10-NEXT: v_xor_b32_e32 v3, -1, v20
-; GFX10-NEXT: v_cndmask_b32_e64 v23, 0, v1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v2, s6
+; GFX10-NEXT: v_and_b32_e32 v23, s7, v20
+; GFX10-NEXT: v_xor_b32_e32 v10, -1, v20
+; GFX10-NEXT: v_cndmask_b32_e64 v24, 0, v1, s4
+; GFX10-NEXT: v_or_b32_e32 v0, v21, v3
; GFX10-NEXT: v_or_b32_e32 v1, v11, v8
; GFX10-NEXT: v_or_b32_e32 v2, v2, v9
-; GFX10-NEXT: v_lshlrev_b64 v[10:11], s8, v[14:15]
; GFX10-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v24
-; GFX10-NEXT: v_and_b32_e32 v25, s7, v3
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 64, v23
+; GFX10-NEXT: v_and_b32_e32 v25, s7, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v16, 31, v14
+; GFX10-NEXT: v_lshlrev_b64 v[12:13], v23, v[6:7]
; GFX10-NEXT: v_lshrrev_b64 v[14:15], 1, v[14:15]
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 64, v24
-; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v24
-; GFX10-NEXT: v_lshrrev_b64 v[12:13], v16, v[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[16:17], v24, v[6:7]
+; GFX10-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5]
; GFX10-NEXT: v_sub_nc_u32_e32 v20, 64, v25
-; GFX10-NEXT: v_or_b32_e32 v8, v8, v10
-; GFX10-NEXT: v_or_b32_e32 v9, v9, v11
-; GFX10-NEXT: v_lshlrev_b64 v[10:11], v24, v[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5]
-; GFX10-NEXT: v_or_b32_e32 v16, v12, v16
-; GFX10-NEXT: v_subrev_nc_u32_e32 v12, 64, v25
+; GFX10-NEXT: v_or_b32_e32 v9, v9, v16
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 64, v23
+; GFX10-NEXT: v_lshlrev_b64 v[16:17], v23, v[4:5]
+; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v23
+; GFX10-NEXT: v_or_b32_e32 v12, v10, v12
+; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v25
; GFX10-NEXT: v_lshrrev_b64 v[18:19], v25, v[8:9]
; GFX10-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15]
-; GFX10-NEXT: v_or_b32_e32 v5, v13, v17
+; GFX10-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5]
+; GFX10-NEXT: v_or_b32_e32 v5, v11, v13
+; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[14:15]
+; GFX10-NEXT: v_cndmask_b32_e32 v13, 0, v16, vcc_lo
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v25
-; GFX10-NEXT: v_lshrrev_b64 v[12:13], v12, v[14:15]
-; GFX10-NEXT: v_cndmask_b32_e32 v16, v3, v16, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v24
-; GFX10-NEXT: v_or_b32_e32 v17, v18, v20
+; GFX10-NEXT: v_or_b32_e32 v16, v18, v20
; GFX10-NEXT: v_or_b32_e32 v18, v19, v21
+; GFX10-NEXT: v_cndmask_b32_e32 v12, v3, v12, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc_lo
; GFX10-NEXT: v_lshrrev_b64 v[3:4], v25, v[14:15]
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v23
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v25
-; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v17, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v18, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v18, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v14, 0, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v5, v7, s6
-; GFX10-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v12, v8, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, v4, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v13, v9, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, v6, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v10, v8, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v4, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v11, v9, s5
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v3, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v16, v6, s6
-; GFX10-NEXT: v_or_b32_e32 v4, v10, v5
-; GFX10-NEXT: v_or_b32_e32 v3, v22, v23
-; GFX10-NEXT: v_or_b32_e32 v5, v11, v8
-; GFX10-NEXT: v_or_b32_e32 v7, v7, v12
+; GFX10-NEXT: v_or_b32_e32 v3, v22, v24
+; GFX10-NEXT: v_or_b32_e32 v4, v13, v5
+; GFX10-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX10-NEXT: v_or_b32_e32 v5, v14, v8
; GFX10-NEXT: v_or_b32_e32 v6, v6, v9
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 743fe18c5da97..65c0da80e20b1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -9,14 +9,13 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX6: ; %bb.0:
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_sub_i32 s3, 0, 7
+; GFX6-NEXT: s_movk_i32 s3, 0x7f
+; GFX6-NEXT: s_and_b32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s0, s0, 1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
-; GFX6-NEXT: s_movk_i32 s3, 0x7f
-; GFX6-NEXT: s_and_b32 s2, s2, s3
; GFX6-NEXT: s_and_b32 s1, s1, s3
+; GFX6-NEXT: v_mul_lo_u32 v1, -7, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
@@ -41,14 +40,13 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX8: ; %bb.0:
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: s_sub_i32 s3, 0, 7
+; GFX8-NEXT: s_movk_i32 s3, 0x7f
+; GFX8-NEXT: s_and_b32 s2, s2, s3
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_lo_u32 v1, s3, v0
-; GFX8-NEXT: s_movk_i32 s3, 0x7f
-; GFX8-NEXT: s_and_b32 s2, s2, s3
; GFX8-NEXT: s_and_b32 s1, s1, s3
+; GFX8-NEXT: v_mul_lo_u32 v1, -7, v0
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
@@ -73,14 +71,13 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s3, 0, 7
+; GFX9-NEXT: s_movk_i32 s3, 0x7f
+; GFX9-NEXT: s_and_b32 s2, s2, s3
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_lo_u32 v1, s3, v0
-; GFX9-NEXT: s_movk_i32 s3, 0x7f
-; GFX9-NEXT: s_and_b32 s2, s2, s3
; GFX9-NEXT: s_and_b32 s1, s1, s3
+; GFX9-NEXT: v_mul_lo_u32 v1, -7, v0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
@@ -104,15 +101,14 @@ define amdgpu_ps i7 @s_fshr_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX10-LABEL: s_fshr_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
-; GFX10-NEXT: s_sub_i32 s3, 0, 7
+; GFX10-NEXT: s_movk_i32 s3, 0x7f
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
+; GFX10-NEXT: s_and_b32 s2, s2, s3
+; GFX10-NEXT: s_and_b32 s1, s1, s3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_lo_u32 v1, s3, v0
-; GFX10-NEXT: s_movk_i32 s3, 0x7f
-; GFX10-NEXT: s_and_b32 s2, s2, s3
-; GFX10-NEXT: s_and_b32 s1, s1, s3
+; GFX10-NEXT: v_mul_lo_u32 v1, -7, v0
; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_hi_u32 v0, s2, v0
@@ -142,12 +138,11 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX6-NEXT: s_sub_i32 s4, 0, 7
; GFX6-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX6-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -174,12 +169,11 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX8-NEXT: s_sub_i32 s4, 0, 7
; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 1, v0
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX8-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX8-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -206,12 +200,11 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX9-NEXT: s_sub_i32 s4, 0, 7
; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 1, v0
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -238,14 +231,13 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
-; GFX10-NEXT: s_sub_i32 s4, 0, 7
; GFX10-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0
; GFX10-NEXT: v_and_b32_e32 v1, 0x7f, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX10-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX10-NEXT: v_mul_lo_u32 v4, -7, v3
; GFX10-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -1211,14 +1203,14 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX6: ; %bb.0:
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_sub_i32 s3, 0, 24
-; GFX6-NEXT: s_lshl_b32 s0, s0, 1
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX6-NEXT: s_mov_b32 s3, 0xffffff
; GFX6-NEXT: s_and_b32 s2, s2, s3
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: s_lshl_b32 s0, s0, 1
; GFX6-NEXT: s_and_b32 s1, s1, s3
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
@@ -1243,14 +1235,14 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX8: ; %bb.0:
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: s_sub_i32 s3, 0, 24
-; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX8-NEXT: s_mov_b32 s3, 0xffffff
; GFX8-NEXT: s_and_b32 s2, s2, s3
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_and_b32 s1, s1, s3
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0
@@ -1275,14 +1267,14 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s3, 0, 24
-; GFX9-NEXT: s_lshl_b32 s0, s0, 1
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_lo_u32 v1, s3, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX9-NEXT: s_mov_b32 s3, 0xffffff
; GFX9-NEXT: s_and_b32 s2, s2, s3
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s1, s1, s3
+; GFX9-NEXT: s_lshl_b32 s0, s0, 1
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, v0
; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
@@ -1305,15 +1297,14 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
; GFX10-LABEL: s_fshr_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX10-NEXT: s_sub_i32 s3, 0, 24
+; GFX10-NEXT: s_mov_b32 s3, 0xffffff
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
+; GFX10-NEXT: s_and_b32 s2, s2, s3
+; GFX10-NEXT: s_and_b32 s1, s1, s3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_lo_u32 v1, s3, v0
-; GFX10-NEXT: s_mov_b32 s3, 0xffffff
-; GFX10-NEXT: s_and_b32 s2, s2, s3
-; GFX10-NEXT: s_and_b32 s1, s1, s3
+; GFX10-NEXT: v_mul_lo_u32 v1, 0xffffffe8, v0
; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_hi_u32 v0, s2, v0
@@ -1342,12 +1333,12 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX6-NEXT: s_sub_i32 s4, 0, 24
+; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffffe8
; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX6-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -1374,12 +1365,12 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX8-NEXT: s_sub_i32 s4, 0, 24
+; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffffe8
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX8-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX8-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -1406,12 +1397,12 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX9-NEXT: s_sub_i32 s4, 0, 24
+; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffffe8
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, v4, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v2, v3
@@ -1437,13 +1428,12 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
-; GFX10-NEXT: s_sub_i32 s4, 0, 24
; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX10-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX10-NEXT: v_mul_lo_u32 v4, 0xffffffe8, v3
; GFX10-NEXT: v_mul_hi_u32 v4, v3, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffffff
@@ -1470,10 +1460,12 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 inreg %amt.arg) {
; GFX6-LABEL: s_fshr_v2i24:
; GFX6: ; %bb.0:
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_movk_i32 s9, 0xff
; GFX6-NEXT: s_mov_b32 s11, 0x80008
; GFX6-NEXT: s_lshr_b32 s6, s0, 16
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX6-NEXT: s_lshr_b32 s8, s1, 8
; GFX6-NEXT: s_and_b32 s1, s1, s9
; GFX6-NEXT: s_lshr_b32 s7, s0, 24
@@ -1481,7 +1473,7 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_bfe_u32 s0, s0, s11
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 8
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: s_or_b32 s0, s10, s0
; GFX6-NEXT: s_or_b32 s1, s7, s1
; GFX6-NEXT: s_and_b32 s7, s8, s9
@@ -1493,7 +1485,8 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_and_b32 s8, s8, s9
; GFX6-NEXT: s_or_b32 s2, s13, s2
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xffffffe8
+; GFX6-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX6-NEXT: s_lshr_b32 s12, s3, 8
; GFX6-NEXT: s_and_b32 s3, s3, s9
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
@@ -1501,108 +1494,105 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_lshl_b32 s3, s3, 8
; GFX6-NEXT: s_or_b32 s2, s2, s8
; GFX6-NEXT: s_and_b32 s8, s12, s9
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_or_b32 s3, s10, s3
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_or_b32 s3, s3, s8
; GFX6-NEXT: s_lshr_b32 s8, s4, 16
; GFX6-NEXT: s_lshr_b32 s10, s4, 24
; GFX6-NEXT: s_and_b32 s13, s4, s9
; GFX6-NEXT: s_bfe_u32 s4, s4, s11
-; GFX6-NEXT: s_sub_i32 s11, 0, 24
-; GFX6-NEXT: v_mul_lo_u32 v1, s11, v0
; GFX6-NEXT: s_lshl_b32 s4, s4, 8
; GFX6-NEXT: s_and_b32 s8, s8, s9
; GFX6-NEXT: s_or_b32 s4, s13, s4
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: s_or_b32 s4, s4, s8
-; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_lshr_b32 s12, s5, 8
-; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX6-NEXT: s_and_b32 s5, s5, s9
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_mul_lo_u32 v2, s11, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, v0
; GFX6-NEXT: s_lshl_b32 s5, s5, 8
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: s_and_b32 s8, s12, s9
; GFX6-NEXT: s_or_b32 s5, s10, s5
-; GFX6-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: s_or_b32 s5, s5, s8
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
-; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
; GFX6-NEXT: s_and_b32 s6, s6, s9
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX6-NEXT: s_mov_b32 s8, 0xffffff
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v0
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v1
; GFX6-NEXT: s_lshl_b32 s4, s6, 17
; GFX6-NEXT: s_lshl_b32 s0, s0, 1
-; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX6-NEXT: v_and_b32_e32 v1, s8, v1
; GFX6-NEXT: s_or_b32 s0, s4, s0
; GFX6-NEXT: v_and_b32_e32 v2, s8, v3
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_lshr_b32_e32 v0, s2, v0
-; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
-; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_lshr_b32_e32 v1, s2, v1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v1
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v0
; GFX6-NEXT: s_lshl_b32 s0, s7, 17
; GFX6-NEXT: s_lshl_b32 s1, s1, 1
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
+; GFX6-NEXT: v_and_b32_e32 v0, v0, v4
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX6-NEXT: v_bfe_u32 v3, v0, 8, 8
+; GFX6-NEXT: v_bfe_u32 v3, v1, 8, 8
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_lshr_b32_e32 v1, s3, v1
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s9, v0
-; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_lshr_b32_e32 v0, s3, v0
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_bfe_u32 v2, v1, 8, 8
; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: v_and_b32_e32 v2, s9, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX6-NEXT: v_bfe_u32 v2, v0, 8, 8
+; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v1
+; GFX6-NEXT: v_readfirstlane_b32 s1, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fshr_v2i24:
; GFX8: ; %bb.0:
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX8-NEXT: s_movk_i32 s10, 0xff
; GFX8-NEXT: s_lshr_b32 s9, s1, 8
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_bfe_u32 s11, 8, 0x100000
; GFX8-NEXT: s_and_b32 s1, s1, s10
; GFX8-NEXT: s_lshr_b32 s6, s0, 8
@@ -1618,15 +1608,15 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_and_b32 s6, s7, s10
; GFX8-NEXT: s_and_b32 s7, s9, s10
+; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX8-NEXT: s_lshr_b32 s9, s2, 16
; GFX8-NEXT: s_lshr_b32 s12, s2, 24
; GFX8-NEXT: s_and_b32 s2, s2, s10
; GFX8-NEXT: s_lshl_b32 s8, s8, s11
; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_and_b32 s8, s9, s10
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_lshr_b32 s13, s3, 8
; GFX8-NEXT: s_and_b32 s3, s3, s10
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
@@ -1634,106 +1624,104 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshl_b32 s3, s3, s11
; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_and_b32 s8, s13, s10
+; GFX8-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX8-NEXT: s_or_b32 s3, s12, s3
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX8-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
; GFX8-NEXT: s_or_b32 s3, s3, s8
; GFX8-NEXT: s_lshr_b32 s8, s4, 8
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s8, s8, s10
+; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_lshr_b32 s9, s4, 16
; GFX8-NEXT: s_lshr_b32 s12, s4, 24
; GFX8-NEXT: s_and_b32 s4, s4, s10
; GFX8-NEXT: s_lshl_b32 s8, s8, s11
; GFX8-NEXT: s_or_b32 s4, s4, s8
; GFX8-NEXT: s_and_b32 s8, s9, s10
-; GFX8-NEXT: s_sub_i32 s9, 0, 24
-; GFX8-NEXT: v_mul_lo_u32 v1, s9, v0
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
-; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX8-NEXT: s_or_b32 s4, s4, s8
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
+; GFX8-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_lshr_b32 s13, s5, 8
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX8-NEXT: s_and_b32 s5, s5, s10
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX8-NEXT: v_mul_lo_u32 v2, v2, v0
; GFX8-NEXT: s_lshl_b32 s5, s5, s11
-; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s4, v1
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: s_and_b32 s8, s13, s10
-; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_mul_lo_u32 v2, s9, v1
; GFX8-NEXT: s_or_b32 s5, s12, s5
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: s_or_b32 s5, s5, s8
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT: v_mul_hi_u32 v0, s5, v0
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2
-; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX8-NEXT: s_mov_b32 s8, 0xffffff
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v0
-; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v1
; GFX8-NEXT: s_lshl_b32 s4, s6, 17
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: v_and_b32_e32 v0, s8, v0
+; GFX8-NEXT: v_and_b32_e32 v1, s8, v1
; GFX8-NEXT: s_or_b32 s0, s4, s0
; GFX8-NEXT: v_and_b32_e32 v2, s8, v3
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s2
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_lshrrev_b32_e64 v1, v1, s2
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s5, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v1
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v0
; GFX8-NEXT: s_lshl_b32 s0, s7, 17
; GFX8-NEXT: s_lshl_b32 s1, s1, 1
-; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
+; GFX8-NEXT: v_and_b32_e32 v0, v0, v4
; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_lshrrev_b32_e64 v1, v1, s3
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s3
+; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: v_mov_b32_e32 v2, 8
-; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX8-NEXT: v_mov_b32_e32 v4, 16
-; GFX8-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
-; GFX8-NEXT: v_and_b32_e32 v3, s10, v1
-; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_sdwa v3, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX8-NEXT: v_and_b32_e32 v3, s10, v0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX8-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v1
+; GFX8-NEXT: v_readfirstlane_b32 s1, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fshr_v2i24:
; GFX9: ; %bb.0:
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: s_movk_i32 s12, 0xff
; GFX9-NEXT: s_lshr_b32 s11, s1, 8
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_bfe_u32 s13, 8, 0x100000
; GFX9-NEXT: s_and_b32 s1, s1, s12
; GFX9-NEXT: s_lshr_b32 s7, s0, 8
@@ -1749,15 +1737,15 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_or_b32 s0, s0, s7
; GFX9-NEXT: s_and_b32 s7, s9, s12
; GFX9-NEXT: s_and_b32 s9, s11, s12
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX9-NEXT: s_lshr_b32 s11, s2, 16
; GFX9-NEXT: s_lshr_b32 s14, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, s12
; GFX9-NEXT: s_lshl_b32 s10, s10, s13
; GFX9-NEXT: s_or_b32 s2, s2, s10
; GFX9-NEXT: s_and_b32 s10, s11, s12
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_lshr_b32 s15, s3, 8
; GFX9-NEXT: s_and_b32 s3, s3, s12
; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
@@ -1765,8 +1753,10 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshl_b32 s3, s3, s13
; GFX9-NEXT: s_or_b32 s2, s2, s10
; GFX9-NEXT: s_and_b32 s10, s15, s12
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX9-NEXT: s_or_b32 s3, s14, s3
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
+; GFX9-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
@@ -1774,218 +1764,209 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshr_b32 s10, s4, 8
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s10, s10, s12
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: s_lshr_b32 s11, s4, 16
; GFX9-NEXT: s_lshr_b32 s14, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, s12
; GFX9-NEXT: s_lshl_b32 s10, s10, s13
; GFX9-NEXT: s_or_b32 s4, s4, s10
; GFX9-NEXT: s_and_b32 s10, s11, s12
-; GFX9-NEXT: s_sub_i32 s11, 0, 24
-; GFX9-NEXT: v_mul_lo_u32 v1, s11, v0
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, v0
; GFX9-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
-; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX9-NEXT: s_or_b32 s4, s4, s10
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX9-NEXT: s_lshr_b32 s15, s5, 8
; GFX9-NEXT: s_and_b32 s5, s5, s12
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
-; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_lshl_b32 s5, s5, s13
-; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX9-NEXT: s_and_b32 s10, s15, s12
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
-; GFX9-NEXT: v_subrev_u32_e32 v2, 24, v0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT: v_mul_lo_u32 v2, s11, v1
; GFX9-NEXT: s_or_b32 s5, s14, s5
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX9-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
; GFX9-NEXT: s_or_b32 s5, s5, s10
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
-; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX9-NEXT: s_mov_b32 s10, 0xffffff
-; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
-; GFX9-NEXT: v_and_b32_e32 v0, s10, v0
+; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
+; GFX9-NEXT: v_and_b32_e32 v1, s10, v1
; GFX9-NEXT: s_lshl_b32 s4, s7, 17
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
-; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
+; GFX9-NEXT: v_sub_u32_e32 v0, s5, v0
; GFX9-NEXT: s_or_b32 s0, s4, s0
; GFX9-NEXT: v_and_b32_e32 v3, s10, v3
-; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s2
-; GFX9-NEXT: v_lshl_or_b32 v0, s0, v3, v0
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s2
+; GFX9-NEXT: v_lshl_or_b32 v1, s0, v3, v1
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: s_bfe_u32 s9, s9, 0x100000
; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffff
-; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
-; GFX9-NEXT: v_and_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
+; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
; GFX9-NEXT: s_lshl_b32 s0, s9, 17
; GFX9-NEXT: s_lshl_b32 s1, s1, 1
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: v_and_b32_e32 v3, v3, v2
-; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s3
-; GFX9-NEXT: v_lshl_or_b32 v1, s0, v3, v1
+; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s3
+; GFX9-NEXT: v_lshl_or_b32 v0, s0, v3, v0
; GFX9-NEXT: s_mov_b32 s6, 8
-; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX9-NEXT: v_and_b32_e32 v3, s12, v1
+; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX9-NEXT: v_and_b32_e32 v3, s12, v0
; GFX9-NEXT: s_mov_b32 s8, 16
-; GFX9-NEXT: v_and_or_b32 v2, v0, s12, v2
-; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX9-NEXT: v_and_or_b32 v2, v1, s12, v2
+; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX9-NEXT: v_or3_b32 v0, v2, v0, v3
-; GFX9-NEXT: v_bfe_u32 v2, v1, 8, 8
-; GFX9-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 8, v2
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_or3_b32 v1, v2, v1, v3
+; GFX9-NEXT: v_bfe_u32 v2, v0, 8, 8
+; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v1
+; GFX9-NEXT: v_readfirstlane_b32 s1, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_fshr_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
-; GFX10-NEXT: s_sub_i32 s13, 0, 24
-; GFX10-NEXT: s_movk_i32 s10, 0xff
+; GFX10-NEXT: s_movk_i32 s8, 0xff
; GFX10-NEXT: s_lshr_b32 s12, s4, 8
+; GFX10-NEXT: s_lshr_b32 s13, s4, 16
+; GFX10-NEXT: s_bfe_u32 s10, 8, 0x100000
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX10-NEXT: s_bfe_u32 s11, 8, 0x100000
-; GFX10-NEXT: s_and_b32 s12, s12, s10
-; GFX10-NEXT: s_lshr_b32 s14, s4, 16
-; GFX10-NEXT: s_lshr_b32 s15, s4, 24
-; GFX10-NEXT: s_and_b32 s4, s4, s10
-; GFX10-NEXT: s_lshl_b32 s12, s12, s11
-; GFX10-NEXT: s_lshr_b32 s16, s5, 8
+; GFX10-NEXT: s_and_b32 s12, s12, s8
+; GFX10-NEXT: s_lshr_b32 s14, s4, 24
+; GFX10-NEXT: s_and_b32 s4, s4, s8
+; GFX10-NEXT: s_lshl_b32 s12, s12, s10
+; GFX10-NEXT: s_and_b32 s13, s13, s8
; GFX10-NEXT: s_or_b32 s4, s4, s12
+; GFX10-NEXT: s_bfe_u32 s12, s13, 0x100000
+; GFX10-NEXT: s_lshr_b32 s15, s5, 8
+; GFX10-NEXT: s_and_b32 s5, s5, s8
+; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX10-NEXT: s_and_b32 s5, s5, s10
; GFX10-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX10-NEXT: s_lshl_b32 s5, s5, s11
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: s_or_b32 s5, s15, s5
-; GFX10-NEXT: s_lshr_b32 s9, s1, 8
-; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX10-NEXT: v_mul_lo_u32 v2, s13, v0
-; GFX10-NEXT: v_mul_lo_u32 v3, s13, v1
-; GFX10-NEXT: s_and_b32 s13, s14, s10
-; GFX10-NEXT: s_and_b32 s1, s1, s10
-; GFX10-NEXT: s_bfe_u32 s12, s13, 0x100000
-; GFX10-NEXT: s_lshr_b32 s6, s0, 8
; GFX10-NEXT: s_lshl_b32 s12, s12, 16
-; GFX10-NEXT: s_lshr_b32 s8, s0, 24
-; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX10-NEXT: s_lshl_b32 s5, s5, s10
+; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: s_or_b32 s4, s4, s12
-; GFX10-NEXT: s_and_b32 s12, s16, s10
-; GFX10-NEXT: s_lshl_b32 s1, s1, s11
+; GFX10-NEXT: s_and_b32 s12, s15, s8
+; GFX10-NEXT: s_or_b32 s5, s14, s5
+; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v1
+; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v0
; GFX10-NEXT: s_bfe_u32 s12, s12, 0x100000
-; GFX10-NEXT: s_or_b32 s1, s8, s1
+; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX10-NEXT: s_lshl_b32 s12, s12, 16
-; GFX10-NEXT: s_and_b32 s6, s6, s10
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
-; GFX10-NEXT: v_mul_hi_u32 v2, v1, v3
+; GFX10-NEXT: s_lshr_b32 s11, s1, 8
; GFX10-NEXT: s_or_b32 s5, s5, s12
-; GFX10-NEXT: s_lshr_b32 s8, s2, 8
+; GFX10-NEXT: s_and_b32 s1, s1, s8
+; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
+; GFX10-NEXT: s_lshr_b32 s6, s0, 8
+; GFX10-NEXT: s_lshr_b32 s9, s0, 24
+; GFX10-NEXT: s_lshl_b32 s1, s1, s10
+; GFX10-NEXT: s_and_b32 s6, s6, s8
+; GFX10-NEXT: s_or_b32 s1, s9, s1
+; GFX10-NEXT: s_lshr_b32 s9, s2, 8
; GFX10-NEXT: s_lshr_b32 s7, s0, 16
-; GFX10-NEXT: v_mul_hi_u32 v0, s4, v0
-; GFX10-NEXT: s_and_b32 s8, s8, s10
-; GFX10-NEXT: s_and_b32 s0, s0, s10
-; GFX10-NEXT: s_lshl_b32 s6, s6, s11
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
+; GFX10-NEXT: v_mul_hi_u32 v2, v0, v3
+; GFX10-NEXT: s_and_b32 s9, s9, s8
+; GFX10-NEXT: s_and_b32 s0, s0, s8
+; GFX10-NEXT: s_lshl_b32 s6, s6, s10
+; GFX10-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX10-NEXT: s_or_b32 s0, s0, s6
-; GFX10-NEXT: s_and_b32 s6, s7, s10
-; GFX10-NEXT: s_and_b32 s7, s9, s10
-; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX10-NEXT: v_mul_hi_u32 v1, s5, v1
-; GFX10-NEXT: s_lshr_b32 s9, s2, 16
+; GFX10-NEXT: s_and_b32 s6, s7, s8
+; GFX10-NEXT: s_and_b32 s7, s11, s8
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
+; GFX10-NEXT: s_lshr_b32 s11, s2, 16
; GFX10-NEXT: s_lshr_b32 s13, s2, 24
-; GFX10-NEXT: s_and_b32 s2, s2, s10
-; GFX10-NEXT: s_lshl_b32 s8, s8, s11
-; GFX10-NEXT: s_lshr_b32 s12, s3, 8
-; GFX10-NEXT: s_or_b32 s2, s2, s8
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, s4, v0
+; GFX10-NEXT: s_and_b32 s2, s2, s8
; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX10-NEXT: s_and_b32 s8, s9, s10
+; GFX10-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX10-NEXT: s_lshl_b32 s9, s9, s10
+; GFX10-NEXT: s_lshr_b32 s12, s3, 8
+; GFX10-NEXT: s_or_b32 s2, s2, s9
+; GFX10-NEXT: s_and_b32 s9, s11, s8
; GFX10-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX10-NEXT: s_bfe_u32 s4, s8, 0x100000
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
+; GFX10-NEXT: s_and_b32 s3, s3, s8
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, s4, v1
+; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX10-NEXT: s_bfe_u32 s4, s9, 0x100000
+; GFX10-NEXT: s_lshl_b32 s3, s3, s10
; GFX10-NEXT: s_lshl_b32 s4, s4, 16
-; GFX10-NEXT: s_and_b32 s3, s3, s10
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, s5, v1
-; GFX10-NEXT: s_or_b32 s2, s2, s4
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX10-NEXT: s_mov_b32 s4, 0xffffff
-; GFX10-NEXT: s_lshl_b32 s3, s3, s11
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
-; GFX10-NEXT: s_and_b32 s5, s12, s10
+; GFX10-NEXT: s_or_b32 s2, s2, s4
+; GFX10-NEXT: s_mov_b32 s4, 0xffffff
+; GFX10-NEXT: v_sub_nc_u32_e32 v0, s5, v0
+; GFX10-NEXT: s_and_b32 s5, s12, s8
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: s_or_b32 s3, s13, s3
; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX10-NEXT: s_lshl_b32 s5, s5, 16
; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX10-NEXT: s_or_b32 s3, s3, s5
; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX10-NEXT: v_mov_b32_e32 v2, 0xffffff
-; GFX10-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX10-NEXT: v_and_b32_e32 v3, s4, v3
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v1
-; GFX10-NEXT: v_and_b32_e32 v1, v1, v2
-; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s2
; GFX10-NEXT: s_lshl_b32 s5, s6, 17
; GFX10-NEXT: s_lshl_b32 s0, s0, 1
-; GFX10-NEXT: v_and_b32_e32 v2, v4, v2
-; GFX10-NEXT: v_lshrrev_b32_e64 v1, v1, s3
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v2, 0xffffff
+; GFX10-NEXT: v_and_b32_e32 v1, s4, v1
; GFX10-NEXT: s_or_b32 s0, s5, s0
+; GFX10-NEXT: v_and_b32_e32 v3, s4, v3
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v0
+; GFX10-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX10-NEXT: v_lshrrev_b32_e64 v1, v1, s2
; GFX10-NEXT: s_lshl_b32 s2, s7, 17
; GFX10-NEXT: s_lshl_b32 s1, s1, 1
-; GFX10-NEXT: v_lshl_or_b32 v0, s0, v3, v0
+; GFX10-NEXT: v_and_b32_e32 v2, v4, v2
+; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s3
+; GFX10-NEXT: v_lshl_or_b32 v1, s0, v3, v1
; GFX10-NEXT: s_or_b32 s0, s2, s1
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, v2, v1
+; GFX10-NEXT: v_lshl_or_b32 v0, s0, v2, v0
; GFX10-NEXT: s_mov_b32 s0, 8
-; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-NEXT: s_mov_b32 s0, 16
-; GFX10-NEXT: v_and_b32_e32 v3, s10, v1
-; GFX10-NEXT: v_bfe_u32 v4, v1, 8, 8
-; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX10-NEXT: v_and_or_b32 v2, v0, s10, v2
-; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX10-NEXT: v_and_b32_e32 v3, s8, v0
+; GFX10-NEXT: v_bfe_u32 v4, v0, 8, 8
+; GFX10-NEXT: v_bfe_u32 v0, v0, 16, 8
+; GFX10-NEXT: v_and_or_b32 v2, v1, s8, v2
+; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v4
-; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v4
+; GFX10-NEXT: v_or3_b32 v1, v2, v1, v3
+; GFX10-NEXT: v_readfirstlane_b32 s1, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v1
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i48 %lhs.arg to <2 x i24>
%rhs = bitcast i48 %rhs.arg to <2 x i24>
@@ -2001,42 +1982,40 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX6-NEXT: s_sub_i32 s4, 0, 24
+; GFX6-NEXT: v_mov_b32_e32 v8, 0xffffffe8
; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v8, 24
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
+; GFX6-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX6-NEXT: v_mul_lo_u32 v7, s4, v6
-; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v7, v8
-; GFX6-NEXT: v_mov_b32_e32 v8, 0xffffff
-; GFX6-NEXT: v_and_b32_e32 v5, v5, v8
-; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX6-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX6-NEXT: v_cvt_u32_f32_e32 v7, v7
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v8
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
+; GFX6-NEXT: v_mul_lo_u32 v9, v8, v7
+; GFX6-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; GFX6-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX6-NEXT: v_mov_b32_e32 v9, 0xffffff
+; GFX6-NEXT: v_and_b32_e32 v5, v5, v9
+; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX6-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX6-NEXT: v_and_b32_e32 v3, v3, v9
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v7
+; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX6-NEXT: v_mul_lo_u32 v6, s4, v7
-; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 23, v4
-; GFX6-NEXT: v_and_b32_e32 v9, v9, v8
-; GFX6-NEXT: v_and_b32_e32 v4, v4, v8
-; GFX6-NEXT: v_mul_hi_u32 v6, v7, v6
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, v9, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX6-NEXT: v_mul_lo_u32 v7, v8, v6
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 23, v4
+; GFX6-NEXT: v_and_b32_e32 v8, v8, v9
+; GFX6-NEXT: v_and_b32_e32 v4, v4, v9
+; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, v8, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX6-NEXT: v_and_b32_e32 v3, v3, v8
; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v5, v6
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2
@@ -2046,8 +2025,8 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT: v_and_b32_e32 v2, v2, v8
-; GFX6-NEXT: v_and_b32_e32 v4, v4, v8
+; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX6-NEXT: v_and_b32_e32 v4, v4, v9
; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
@@ -2058,42 +2037,40 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX8-NEXT: s_sub_i32 s4, 0, 24
+; GFX8-NEXT: v_mov_b32_e32 v8, 0xffffffe8
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v8, 24
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
+; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX8-NEXT: v_mul_lo_u32 v7, s4, v6
-; GFX8-NEXT: v_mul_hi_u32 v7, v6, v7
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
-; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v7, v8
-; GFX8-NEXT: v_mov_b32_e32 v8, 0xffffff
-; GFX8-NEXT: v_and_b32_e32 v5, v5, v8
-; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX8-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v7
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v8
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6
-; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
+; GFX8-NEXT: v_mul_lo_u32 v9, v8, v7
+; GFX8-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9
+; GFX8-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX8-NEXT: v_mov_b32_e32 v9, 0xffffff
+; GFX8-NEXT: v_and_b32_e32 v5, v5, v9
+; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX8-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX8-NEXT: v_and_b32_e32 v3, v3, v9
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v7
+; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT: v_mul_lo_u32 v6, s4, v7
-; GFX8-NEXT: v_sub_u32_e32 v9, vcc, 23, v4
-; GFX8-NEXT: v_and_b32_e32 v9, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v4, v4, v8
-; GFX8-NEXT: v_mul_hi_u32 v6, v7, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, v9, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX8-NEXT: v_mul_lo_u32 v7, v8, v6
+; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 23, v4
+; GFX8-NEXT: v_and_b32_e32 v8, v8, v9
+; GFX8-NEXT: v_and_b32_e32 v4, v4, v9
+; GFX8-NEXT: v_mul_hi_u32 v7, v6, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, v8, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX8-NEXT: v_and_b32_e32 v3, v3, v8
; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v5, v6
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 24, v2
@@ -2103,8 +2080,8 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, v2, v8
-; GFX8-NEXT: v_and_b32_e32 v4, v4, v8
+; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX8-NEXT: v_and_b32_e32 v4, v4, v9
; GFX8-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v2, v3
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
@@ -2115,43 +2092,41 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX9-NEXT: s_sub_i32 s4, 0, 24
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v8, 24
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v8, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, 0xffffffe8
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX9-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_mul_lo_u32 v9, v8, v7
+; GFX9-NEXT: v_mul_lo_u32 v8, v8, v6
+; GFX9-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
+; GFX9-NEXT: v_mul_hi_u32 v7, v4, v7
; GFX9-NEXT: v_mov_b32_e32 v9, 0xffffff
-; GFX9-NEXT: v_mul_lo_u32 v7, s4, v6
; GFX9-NEXT: v_and_b32_e32 v5, v5, v9
+; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX9-NEXT: v_and_b32_e32 v2, v2, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX9-NEXT: v_mul_hi_u32 v7, v6, v7
; GFX9-NEXT: v_and_b32_e32 v3, v3, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_add_u32_e32 v6, v6, v7
-; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v8
-; GFX9-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX9-NEXT: v_mul_lo_u32 v8, s4, v7
-; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX9-NEXT: v_mul_hi_u32 v8, v7, v8
-; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
-; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
+; GFX9-NEXT: v_sub_u32_e32 v4, v4, v7
+; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_add_u32_e32 v7, v7, v8
-; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX9-NEXT: v_sub_u32_e32 v6, 23, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX9-NEXT: v_sub_u32_e32 v7, 23, v4
; GFX9-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX9-NEXT: v_and_b32_e32 v6, v6, v9
+; GFX9-NEXT: v_and_b32_e32 v7, v7, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v4, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, v6, v2
-; GFX9-NEXT: v_sub_u32_e32 v2, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, v7, v2
+; GFX9-NEXT: v_sub_u32_e32 v2, v5, v6
; GFX9-NEXT: v_subrev_u32_e32 v4, 24, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2170,33 +2145,30 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
-; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
-; GFX10-NEXT: s_sub_i32 s4, 0, 24
; GFX10-NEXT: v_mov_b32_e32 v10, 0xffffff
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GFX10-NEXT: v_and_b32_e32 v5, v5, v10
; GFX10-NEXT: v_and_b32_e32 v2, v2, v10
; GFX10-NEXT: v_and_b32_e32 v3, v3, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
-; GFX10-NEXT: v_mul_lo_u32 v8, s4, v6
-; GFX10-NEXT: v_mul_lo_u32 v9, s4, v7
-; GFX10-NEXT: v_mul_hi_u32 v8, v6, v8
-; GFX10-NEXT: v_mul_hi_u32 v9, v7, v9
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v9
-; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
-; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
-; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v7
+; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v6
+; GFX10-NEXT: v_mul_hi_u32 v8, v7, v8
+; GFX10-NEXT: v_mul_hi_u32 v9, v6, v9
+; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v9
+; GFX10-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX10-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7
+; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v7
+; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v6
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
@@ -3057,12 +3029,9 @@ define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <
; GFX6-NEXT: s_lshl_b32 s0, s0, s5
; GFX6-NEXT: s_lshl_b32 s1, s1, s5
; GFX6-NEXT: s_and_b32 s5, s3, s6
-; GFX6-NEXT: s_lshr_b32 s7, s7, 1
-; GFX6-NEXT: s_bfe_u32 s8, 14, 0x100000
-; GFX6-NEXT: s_lshr_b32 s5, s5, 1
; GFX6-NEXT: s_lshl_b32 s2, s2, 1
-; GFX6-NEXT: s_lshr_b32 s7, s7, s8
-; GFX6-NEXT: s_lshr_b32 s5, s5, s8
+; GFX6-NEXT: s_lshr_b32 s7, s7, 15
+; GFX6-NEXT: s_lshr_b32 s5, s5, 15
; GFX6-NEXT: s_xor_b32 s4, s4, -1
; GFX6-NEXT: s_and_b32 s2, s2, s6
; GFX6-NEXT: s_or_b32 s0, s0, s7
@@ -3096,17 +3065,15 @@ define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s5, 1, 0x100000
; GFX8-NEXT: s_bfe_u32 s6, s1, 0x100000
-; GFX8-NEXT: s_lshr_b32 s6, s6, s5
-; GFX8-NEXT: s_bfe_u32 s7, 14, 0x100000
+; GFX8-NEXT: s_bfe_u32 s7, 15, 0x100000
; GFX8-NEXT: s_lshr_b32 s3, s0, 16
; GFX8-NEXT: s_lshr_b32 s4, s1, 16
; GFX8-NEXT: s_lshl_b32 s0, s0, s5
; GFX8-NEXT: s_lshr_b32 s6, s6, s7
-; GFX8-NEXT: s_or_b32 s0, s0, s6
-; GFX8-NEXT: s_lshr_b32 s6, s4, s5
; GFX8-NEXT: s_lshl_b32 s1, s1, s5
+; GFX8-NEXT: s_or_b32 s0, s0, s6
+; GFX8-NEXT: s_lshr_b32 s6, s4, s7
; GFX8-NEXT: s_lshl_b32 s3, s3, s5
-; GFX8-NEXT: s_lshr_b32 s6, s6, s7
; GFX8-NEXT: s_xor_b32 s2, s2, -1
; GFX8-NEXT: s_and_b32 s7, s2, 15
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
@@ -3200,16 +3167,13 @@ define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
; GFX6-NEXT: v_or_b32_e32 v4, v5, v4
; GFX6-NEXT: v_and_b32_e32 v5, s5, v2
; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, 1, v5
-; GFX6-NEXT: s_bfe_u32 s6, 14, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, s6, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, 15, v5
; GFX6-NEXT: v_or_b32_e32 v0, v0, v5
; GFX6-NEXT: v_and_b32_e32 v5, s5, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, 1, v5
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v5, s6, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, 15, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 1, v2
; GFX6-NEXT: v_and_b32_e32 v7, 15, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
@@ -3239,15 +3203,14 @@ define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
; GFX8-LABEL: v_fshr_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, 1, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v3, 1, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, 14, v4
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 15, v1
+; GFX8-NEXT: v_mov_b32_e32 v5, 15
; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
; GFX8-NEXT: v_mov_b32_e32 v4, 1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v5, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v5, 14, v5
+; GFX8-NEXT: v_lshrrev_b16_sdwa v5, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
; GFX8-NEXT: v_lshlrev_b16_e32 v5, 1, v1
; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
@@ -3305,25 +3268,19 @@ define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: v_fshr_v2i16_4_8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_sub_i32 s4, 0, 4
-; GFX6-NEXT: s_and_b32 s6, s4, 15
-; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, s6, v0
-; GFX6-NEXT: s_mov_b32 s6, 0xffff
-; GFX6-NEXT: s_xor_b32 s4, s4, -1
-; GFX6-NEXT: v_and_b32_e32 v2, s6, v2
-; GFX6-NEXT: s_sub_i32 s5, 0, 8
+; GFX6-NEXT: s_bfe_u32 s4, 12, 0x100000
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
+; GFX6-NEXT: s_mov_b32 s4, 0xffff
+; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2
-; GFX6-NEXT: s_and_b32 s4, s5, 15
+; GFX6-NEXT: s_bfe_u32 s5, 3, 0x100000
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, s5, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s6, v3
-; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX6-NEXT: s_xor_b32 s5, s5, -1
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
+; GFX6-NEXT: s_bfe_u32 s5, 8, 0x100000
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT: s_bfe_u32 s4, s5, 0x100000
+; GFX6-NEXT: s_bfe_u32 s4, 7, 0x100000
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, s5, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, s4, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -3331,25 +3288,17 @@ define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX8-LABEL: v_fshr_v2i16_4_8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_sub_i32 s4, 0, 4
-; GFX8-NEXT: s_and_b32 s6, s4, 15
-; GFX8-NEXT: s_sub_i32 s5, 0, 8
-; GFX8-NEXT: s_xor_b32 s4, s4, -1
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, s4, v3
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, s6, v0
-; GFX8-NEXT: s_and_b32 s4, s5, 15
-; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX8-NEXT: v_mov_b32_e32 v3, s4
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_mov_b32_e32 v3, 1
-; GFX8-NEXT: s_xor_b32 s5, s5, -1
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 12, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 4, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX8-NEXT: v_mov_b32_e32 v3, 8
+; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v2
; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, s5, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v1, 16
-; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_v2i16_4_8:
@@ -3358,14 +3307,14 @@ define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, 16
; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 16
+; GFX9-NEXT: s_mov_b32 s4, 0x4f7ffffe
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX9-NEXT: s_sub_i32 s4, 0, 16
-; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX9-NEXT: v_mul_f32_e32 v2, s4, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, s4, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT: v_mul_lo_u32 v4, s4, v2
-; GFX9-NEXT: v_mul_lo_u32 v5, s4, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, -16, v2
+; GFX9-NEXT: v_mul_lo_u32 v5, -16, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
@@ -3403,15 +3352,15 @@ define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v2, 16
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 16
-; GFX10-NEXT: s_sub_i32 s4, 0, 16
+; GFX10-NEXT: s_mov_b32 s4, 0x4f7ffffe
; GFX10-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX10-NEXT: v_mul_f32_e32 v2, s4, v2
+; GFX10-NEXT: v_mul_f32_e32 v3, s4, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX10-NEXT: v_mul_lo_u32 v4, s4, v2
-; GFX10-NEXT: v_mul_lo_u32 v5, s4, v3
+; GFX10-NEXT: v_mul_lo_u32 v4, -16, v2
+; GFX10-NEXT: v_mul_lo_u32 v5, -16, v3
; GFX10-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX10-NEXT: v_mul_hi_u32 v5, v3, v5
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v4
@@ -3448,18 +3397,16 @@ define <2 x i16> @v_fshr_v2i16_4_8(<2 x i16> %lhs, <2 x i16> %rhs) {
define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <2 x i16> %amt) {
; GFX6-LABEL: v_fshr_v2i16_ssv:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b32 s5, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX6-NEXT: s_and_b32 s6, s2, s5
; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX6-NEXT: s_mov_b32 s5, 0xffff
+; GFX6-NEXT: s_and_b32 s6, s2, s5
; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000
; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX6-NEXT: s_lshr_b32 s6, s6, 1
-; GFX6-NEXT: s_bfe_u32 s7, 14, 0x100000
; GFX6-NEXT: v_and_b32_e32 v2, 15, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, s4
-; GFX6-NEXT: s_lshr_b32 s6, s6, s7
+; GFX6-NEXT: s_lshr_b32 s6, s6, 15
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX6-NEXT: s_or_b32 s0, s0, s6
@@ -3471,16 +3418,15 @@ define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %
; GFX6-NEXT: s_lshr_b32 s0, s0, 1
; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
-; GFX6-NEXT: s_lshl_b32 s1, s1, s4
-; GFX6-NEXT: s_and_b32 s4, s3, s5
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-NEXT: v_and_b32_e32 v2, 15, v1
-; GFX6-NEXT: s_lshr_b32 s4, s4, 1
; GFX6-NEXT: v_xor_b32_e32 v1, -1, v1
+; GFX6-NEXT: s_lshl_b32 s1, s1, s4
+; GFX6-NEXT: s_and_b32 s4, s3, s5
; GFX6-NEXT: s_lshl_b32 s3, s3, 1
; GFX6-NEXT: v_and_b32_e32 v1, 15, v1
; GFX6-NEXT: s_and_b32 s0, s3, s5
-; GFX6-NEXT: s_lshr_b32 s4, s4, s7
+; GFX6-NEXT: s_lshr_b32 s4, s4, 15
; GFX6-NEXT: s_or_b32 s1, s1, s4
; GFX6-NEXT: v_bfe_u32 v2, v2, 0, 16
; GFX6-NEXT: s_lshr_b32 s0, s0, 1
@@ -3498,8 +3444,7 @@ define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s4, 1, 0x100000
; GFX8-NEXT: s_bfe_u32 s5, s1, 0x100000
-; GFX8-NEXT: s_lshr_b32 s5, s5, s4
-; GFX8-NEXT: s_bfe_u32 s6, 14, 0x100000
+; GFX8-NEXT: s_bfe_u32 s6, 15, 0x100000
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX8-NEXT: s_lshl_b32 s0, s0, s4
@@ -3514,15 +3459,14 @@ define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %
; GFX8-NEXT: s_bfe_u32 s0, s1, 0x100000
; GFX8-NEXT: v_and_b32_e32 v0, 15, v0
; GFX8-NEXT: s_lshr_b32 s0, s0, s4
-; GFX8-NEXT: s_lshr_b32 s5, s3, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0
+; GFX8-NEXT: s_lshr_b32 s5, s3, s6
; GFX8-NEXT: s_lshl_b32 s3, s3, s4
+; GFX8-NEXT: s_lshl_b32 s2, s2, s4
; GFX8-NEXT: s_bfe_u32 s0, s3, 0x100000
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: v_and_b32_e32 v2, 15, v1
; GFX8-NEXT: v_xor_b32_e32 v1, -1, v1
-; GFX8-NEXT: s_lshl_b32 s2, s2, s4
-; GFX8-NEXT: s_lshr_b32 s5, s5, s6
; GFX8-NEXT: s_or_b32 s2, s2, s5
; GFX8-NEXT: v_and_b32_e32 v1, 15, v1
; GFX8-NEXT: s_lshr_b32 s0, s0, s4
@@ -3572,20 +3516,17 @@ define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <
; GFX6-LABEL: v_fshr_v2i16_svs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s4, 0xffff
-; GFX6-NEXT: v_and_b32_e32 v2, s4, v0
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s2, s2, s4
-; GFX6-NEXT: v_and_b32_e32 v3, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v2, s4, v0
; GFX6-NEXT: s_or_b32 s2, s3, s2
; GFX6-NEXT: s_bfe_u32 s3, 1, 0x100000
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT: s_bfe_u32 s5, 14, 0x100000
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 1, v3
+; GFX6-NEXT: v_and_b32_e32 v3, s4, v1
; GFX6-NEXT: s_lshl_b32 s0, s0, s3
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, s5, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 15, v2
; GFX6-NEXT: v_or_b32_e32 v2, s0, v2
; GFX6-NEXT: s_lshl_b32 s0, s1, s3
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, s5, v3
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 15, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: v_or_b32_e32 v3, s0, v3
; GFX6-NEXT: s_xor_b32 s0, s2, -1
@@ -3617,34 +3558,33 @@ define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <
;
; GFX8-LABEL: v_fshr_v2i16_svs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v0
-; GFX8-NEXT: v_mov_b32_e32 v2, 1
; GFX8-NEXT: s_bfe_u32 s3, 1, 0x100000
-; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v2, 15
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: s_lshl_b32 s0, s0, s3
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, 14, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 15, v0
; GFX8-NEXT: v_or_b32_e32 v1, s0, v1
; GFX8-NEXT: s_lshl_b32 s0, s2, s3
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, 14, v3
-; GFX8-NEXT: v_or_b32_e32 v3, s0, v3
+; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshlrev_b16_e32 v3, 1, v0
+; GFX8-NEXT: v_or_b32_e32 v2, s0, v2
; GFX8-NEXT: s_xor_b32 s0, s1, -1
-; GFX8-NEXT: v_lshlrev_b16_e32 v4, 1, v0
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v4, 1
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: s_and_b32 s2, s0, 15
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: s_andn2_b32 s0, 15, s0
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v4
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, s0, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v1, s2, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, s0, v3
; GFX8-NEXT: s_and_b32 s0, s1, 15
; GFX8-NEXT: s_andn2_b32 s1, 15, s1
; GFX8-NEXT: v_lshrrev_b16_e32 v0, 1, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, s0, v3
+; GFX8-NEXT: v_lshlrev_b16_e32 v2, s0, v2
; GFX8-NEXT: v_lshrrev_b16_e32 v0, s1, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, s2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: v_mov_b32_e32 v2, 16
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
@@ -3701,12 +3641,9 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s3, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s3, v1
; GFX6-NEXT: s_and_b32 s3, s1, s4
-; GFX6-NEXT: s_lshr_b32 s5, s5, 1
-; GFX6-NEXT: s_bfe_u32 s6, 14, 0x100000
-; GFX6-NEXT: s_lshr_b32 s3, s3, 1
; GFX6-NEXT: s_lshl_b32 s0, s0, 1
-; GFX6-NEXT: s_lshr_b32 s5, s5, s6
-; GFX6-NEXT: s_lshr_b32 s3, s3, s6
+; GFX6-NEXT: s_lshr_b32 s5, s5, 15
+; GFX6-NEXT: s_lshr_b32 s3, s3, 15
; GFX6-NEXT: s_xor_b32 s2, s2, -1
; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: v_or_b32_e32 v0, s5, v0
@@ -3739,35 +3676,33 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
; GFX8-LABEL: v_fshr_v2i16_vss:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s3, s0, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, 1, 0x100000
-; GFX8-NEXT: s_lshr_b32 s3, s3, s4
-; GFX8-NEXT: s_bfe_u32 s5, 14, 0x100000
+; GFX8-NEXT: s_bfe_u32 s4, 15, 0x100000
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 1, v0
-; GFX8-NEXT: s_lshr_b32 s3, s3, s5
-; GFX8-NEXT: v_or_b32_e32 v1, s3, v1
-; GFX8-NEXT: s_lshr_b32 s3, s2, s4
+; GFX8-NEXT: s_lshr_b32 s3, s3, s4
; GFX8-NEXT: v_mov_b32_e32 v2, 1
-; GFX8-NEXT: s_lshl_b32 s0, s0, s4
+; GFX8-NEXT: v_or_b32_e32 v1, s3, v1
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: s_lshr_b32 s3, s3, s5
+; GFX8-NEXT: s_lshr_b32 s3, s2, s4
+; GFX8-NEXT: v_or_b32_e32 v0, s3, v0
+; GFX8-NEXT: s_bfe_u32 s3, 1, 0x100000
+; GFX8-NEXT: s_lshl_b32 s0, s0, s3
; GFX8-NEXT: s_xor_b32 s1, s1, -1
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: v_or_b32_e32 v0, s3, v0
; GFX8-NEXT: s_and_b32 s5, s1, 15
-; GFX8-NEXT: s_lshr_b32 s3, s1, 16
+; GFX8-NEXT: s_lshr_b32 s4, s1, 16
; GFX8-NEXT: s_andn2_b32 s1, 15, s1
-; GFX8-NEXT: s_lshr_b32 s0, s0, s4
+; GFX8-NEXT: s_lshr_b32 s0, s0, s3
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshr_b32 s0, s0, s1
; GFX8-NEXT: v_lshlrev_b16_e32 v1, s5, v1
; GFX8-NEXT: v_or_b32_e32 v1, s0, v1
-; GFX8-NEXT: s_and_b32 s0, s3, 15
-; GFX8-NEXT: s_lshl_b32 s2, s2, s4
-; GFX8-NEXT: s_andn2_b32 s1, 15, s3
+; GFX8-NEXT: s_and_b32 s0, s4, 15
+; GFX8-NEXT: s_lshl_b32 s2, s2, s3
+; GFX8-NEXT: s_andn2_b32 s1, 15, s4
; GFX8-NEXT: v_lshlrev_b16_e32 v0, s0, v0
; GFX8-NEXT: s_bfe_u32 s0, s2, 0x100000
-; GFX8-NEXT: s_lshr_b32 s0, s0, s4
+; GFX8-NEXT: s_lshr_b32 s0, s0, s3
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshr_b32 s0, s0, s1
; GFX8-NEXT: v_or_b32_e32 v0, s0, v0
@@ -3838,31 +3773,28 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX6-NEXT: s_and_b32 s8, s8, s12
; GFX6-NEXT: s_or_b32 s8, s9, s8
; GFX6-NEXT: s_lshl_b32 s9, s11, 16
-; GFX6-NEXT: s_and_b32 s11, s4, s12
; GFX6-NEXT: s_and_b32 s10, s10, s12
+; GFX6-NEXT: s_and_b32 s11, s4, s12
; GFX6-NEXT: s_or_b32 s9, s9, s10
; GFX6-NEXT: s_bfe_u32 s10, 1, 0x100000
-; GFX6-NEXT: s_lshr_b32 s11, s11, 1
-; GFX6-NEXT: s_bfe_u32 s13, 14, 0x100000
; GFX6-NEXT: s_lshl_b32 s0, s0, s10
-; GFX6-NEXT: s_lshr_b32 s11, s11, s13
+; GFX6-NEXT: s_lshr_b32 s11, s11, 15
; GFX6-NEXT: s_or_b32 s0, s0, s11
; GFX6-NEXT: s_and_b32 s11, s5, s12
-; GFX6-NEXT: s_lshr_b32 s11, s11, 1
; GFX6-NEXT: s_lshl_b32 s4, s4, 1
; GFX6-NEXT: s_xor_b32 s8, s8, -1
; GFX6-NEXT: s_lshl_b32 s1, s1, s10
-; GFX6-NEXT: s_lshr_b32 s11, s11, s13
-; GFX6-NEXT: s_and_b32 s14, s8, 15
+; GFX6-NEXT: s_lshr_b32 s11, s11, 15
+; GFX6-NEXT: s_and_b32 s13, s8, 15
; GFX6-NEXT: s_and_b32 s4, s4, s12
; GFX6-NEXT: s_or_b32 s1, s1, s11
; GFX6-NEXT: s_lshr_b32 s11, s8, 16
; GFX6-NEXT: s_andn2_b32 s8, 15, s8
-; GFX6-NEXT: s_bfe_u32 s14, s14, 0x100000
+; GFX6-NEXT: s_bfe_u32 s13, s13, 0x100000
; GFX6-NEXT: s_lshr_b32 s4, s4, 1
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: s_lshr_b32 s4, s4, s8
-; GFX6-NEXT: s_lshl_b32 s0, s0, s14
+; GFX6-NEXT: s_lshl_b32 s0, s0, s13
; GFX6-NEXT: s_or_b32 s0, s0, s4
; GFX6-NEXT: s_and_b32 s4, s11, 15
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
@@ -3880,13 +3812,11 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, s10
; GFX6-NEXT: s_and_b32 s2, s6, s12
-; GFX6-NEXT: s_lshr_b32 s2, s2, 1
-; GFX6-NEXT: s_lshr_b32 s2, s2, s13
+; GFX6-NEXT: s_lshr_b32 s2, s2, 15
; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, s10
; GFX6-NEXT: s_and_b32 s3, s7, s12
-; GFX6-NEXT: s_lshr_b32 s3, s3, 1
-; GFX6-NEXT: s_lshr_b32 s3, s3, s13
+; GFX6-NEXT: s_lshr_b32 s3, s3, 15
; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s6, 1
; GFX6-NEXT: s_xor_b32 s5, s9, -1
@@ -3920,18 +3850,16 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s8, 1, 0x100000
; GFX8-NEXT: s_bfe_u32 s9, s2, 0x100000
-; GFX8-NEXT: s_lshr_b32 s9, s9, s8
-; GFX8-NEXT: s_bfe_u32 s10, 14, 0x100000
+; GFX8-NEXT: s_bfe_u32 s10, 15, 0x100000
; GFX8-NEXT: s_lshr_b32 s6, s0, 16
; GFX8-NEXT: s_lshr_b32 s7, s2, 16
; GFX8-NEXT: s_lshl_b32 s0, s0, s8
; GFX8-NEXT: s_lshr_b32 s9, s9, s10
-; GFX8-NEXT: s_or_b32 s0, s0, s9
-; GFX8-NEXT: s_lshr_b32 s9, s7, s8
; GFX8-NEXT: s_lshl_b32 s2, s2, s8
-; GFX8-NEXT: s_xor_b32 s4, s4, -1
+; GFX8-NEXT: s_or_b32 s0, s0, s9
+; GFX8-NEXT: s_lshr_b32 s9, s7, s10
; GFX8-NEXT: s_lshl_b32 s6, s6, s8
-; GFX8-NEXT: s_lshr_b32 s9, s9, s10
+; GFX8-NEXT: s_xor_b32 s4, s4, -1
; GFX8-NEXT: s_and_b32 s11, s4, 15
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX8-NEXT: s_or_b32 s6, s6, s9
@@ -3955,7 +3883,6 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX8-NEXT: s_or_b32 s2, s2, s4
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX8-NEXT: s_bfe_u32 s6, s3, 0x100000
-; GFX8-NEXT: s_lshr_b32 s6, s6, s8
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s2, s2, 16
; GFX8-NEXT: s_or_b32 s0, s0, s2
@@ -3963,12 +3890,11 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX8-NEXT: s_lshr_b32 s4, s3, 16
; GFX8-NEXT: s_lshl_b32 s1, s1, s8
; GFX8-NEXT: s_lshr_b32 s6, s6, s10
-; GFX8-NEXT: s_or_b32 s1, s1, s6
-; GFX8-NEXT: s_lshr_b32 s6, s4, s8
; GFX8-NEXT: s_lshl_b32 s3, s3, s8
-; GFX8-NEXT: s_xor_b32 s5, s5, -1
+; GFX8-NEXT: s_or_b32 s1, s1, s6
+; GFX8-NEXT: s_lshr_b32 s6, s4, s10
; GFX8-NEXT: s_lshl_b32 s2, s2, s8
-; GFX8-NEXT: s_lshr_b32 s6, s6, s10
+; GFX8-NEXT: s_xor_b32 s5, s5, -1
; GFX8-NEXT: s_and_b32 s7, s5, 15
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX8-NEXT: s_or_b32 s2, s2, s6
@@ -4101,19 +4027,16 @@ define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX6-NEXT: v_lshlrev_b32_e32 v9, 16, v11
; GFX6-NEXT: v_and_b32_e32 v10, v10, v12
; GFX6-NEXT: s_mov_b32 s5, 0xffff
+; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000
; GFX6-NEXT: v_or_b32_e32 v9, v9, v10
; GFX6-NEXT: v_and_b32_e32 v10, s5, v4
-; GFX6-NEXT: s_bfe_u32 s4, 1, 0x100000
-; GFX6-NEXT: v_lshrrev_b32_e32 v10, 1, v10
-; GFX6-NEXT: s_bfe_u32 s6, 14, 0x100000
; GFX6-NEXT: v_lshlrev_b32_e32 v0, s4, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v10, s6, v10
+; GFX6-NEXT: v_lshrrev_b32_e32 v10, 15, v10
; GFX6-NEXT: v_or_b32_e32 v0, v0, v10
; GFX6-NEXT: v_and_b32_e32 v10, s5, v5
-; GFX6-NEXT: v_lshrrev_b32_e32 v10, 1, v10
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v1, s4, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v10, s6, v10
+; GFX6-NEXT: v_lshrrev_b32_e32 v10, 15, v10
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_and_b32_e32 v11, 15, v8
; GFX6-NEXT: v_or_b32_e32 v1, v1, v10
@@ -4139,14 +4062,12 @@ define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v5, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v4
; GFX6-NEXT: v_and_b32_e32 v4, v6, v12
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, s4, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, s6, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 15, v4
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
; GFX6-NEXT: v_and_b32_e32 v4, v7, v12
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, s4, v3
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, s6, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 15, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v6
; GFX6-NEXT: v_xor_b32_e32 v6, -1, v9
@@ -4177,25 +4098,24 @@ define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX8-LABEL: v_fshr_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v6, 1, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, 14, v7
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, 15, v2
; GFX8-NEXT: v_or_b32_e32 v6, v6, v7
; GFX8-NEXT: v_mov_b32_e32 v7, 1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v8, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v8, 15
; GFX8-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v8, 14, v8
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v8
-; GFX8-NEXT: v_lshlrev_b16_e32 v8, 1, v2
+; GFX8-NEXT: v_lshrrev_b16_sdwa v9, v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v9
+; GFX8-NEXT: v_lshlrev_b16_e32 v9, 1, v2
; GFX8-NEXT: v_lshlrev_b16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_and_b32_e32 v9, 15, v4
+; GFX8-NEXT: v_and_b32_e32 v10, 15, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v4
; GFX8-NEXT: v_xor_b32_e32 v4, -1, v4
; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT: v_lshrrev_b16_e32 v8, 1, v8
-; GFX8-NEXT: v_lshlrev_b16_e32 v6, v9, v6
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, v4, v8
+; GFX8-NEXT: v_lshrrev_b16_e32 v9, 1, v9
+; GFX8-NEXT: v_lshlrev_b16_e32 v6, v10, v6
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, v4, v9
; GFX8-NEXT: v_or_b32_e32 v4, v6, v4
; GFX8-NEXT: v_and_b32_e32 v6, 15, v7
; GFX8-NEXT: v_xor_b32_e32 v7, -1, v7
@@ -4206,16 +4126,14 @@ define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_mov_b32_e32 v2, 16
; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX8-NEXT: v_lshrrev_b16_e32 v6, 1, v3
; GFX8-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 1, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v6, 14, v6
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 15, v3
; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
; GFX8-NEXT: v_mov_b32_e32 v6, 1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v7, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_xor_b32_e32 v5, -1, v5
; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, 14, v7
+; GFX8-NEXT: v_lshrrev_b16_sdwa v7, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_xor_b32_e32 v5, -1, v5
; GFX8-NEXT: v_or_b32_e32 v1, v1, v7
; GFX8-NEXT: v_lshlrev_b16_e32 v7, 1, v3
; GFX8-NEXT: v_lshlrev_b16_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
@@ -4840,25 +4758,25 @@ define <2 x i64> @v_fshr_v2i64(<2 x i64> %lhs, <2 x i64> %rhs, <2 x i64> %amt) {
define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg %amt) {
; GFX6-LABEL: s_fshr_i128:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b64 s[10:11], 0x7f
+; GFX6-NEXT: s_movk_i32 s10, 0x7f
+; GFX6-NEXT: s_mov_b32 s11, 0
; GFX6-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX6-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
-; GFX6-NEXT: s_sub_i32 s9, 64, 1
-; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s9
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
+; GFX6-NEXT: s_lshl_b64 s[14:15], s[0:1], 1
+; GFX6-NEXT: s_lshr_b32 s10, s1, 31
+; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], 1
+; GFX6-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1]
; GFX6-NEXT: s_sub_i32 s13, s8, 64
; GFX6-NEXT: s_sub_i32 s9, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64
; GFX6-NEXT: s_cselect_b32 s16, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b32 s17, 1, 0
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[10:11], s8
-; GFX6-NEXT: s_lshr_b64 s[14:15], s[10:11], s9
+; GFX6-NEXT: s_lshl_b64 s[2:3], s[14:15], s8
+; GFX6-NEXT: s_lshr_b64 s[10:11], s[14:15], s9
; GFX6-NEXT: s_lshl_b64 s[8:9], s[0:1], s8
-; GFX6-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9]
-; GFX6-NEXT: s_lshl_b64 s[10:11], s[10:11], s13
+; GFX6-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
+; GFX6-NEXT: s_lshl_b64 s[10:11], s[14:15], s13
; GFX6-NEXT: s_cmp_lg_u32 s16, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
@@ -4887,25 +4805,25 @@ define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
;
; GFX8-LABEL: s_fshr_i128:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_mov_b64 s[10:11], 0x7f
+; GFX8-NEXT: s_movk_i32 s10, 0x7f
+; GFX8-NEXT: s_mov_b32 s11, 0
; GFX8-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX8-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
-; GFX8-NEXT: s_sub_i32 s9, 64, 1
-; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s9
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
+; GFX8-NEXT: s_lshl_b64 s[14:15], s[0:1], 1
+; GFX8-NEXT: s_lshr_b32 s10, s1, 31
+; GFX8-NEXT: s_lshl_b64 s[0:1], s[2:3], 1
+; GFX8-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1]
; GFX8-NEXT: s_sub_i32 s13, s8, 64
; GFX8-NEXT: s_sub_i32 s9, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64
; GFX8-NEXT: s_cselect_b32 s16, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b32 s17, 1, 0
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[10:11], s8
-; GFX8-NEXT: s_lshr_b64 s[14:15], s[10:11], s9
+; GFX8-NEXT: s_lshl_b64 s[2:3], s[14:15], s8
+; GFX8-NEXT: s_lshr_b64 s[10:11], s[14:15], s9
; GFX8-NEXT: s_lshl_b64 s[8:9], s[0:1], s8
-; GFX8-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9]
-; GFX8-NEXT: s_lshl_b64 s[10:11], s[10:11], s13
+; GFX8-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
+; GFX8-NEXT: s_lshl_b64 s[10:11], s[14:15], s13
; GFX8-NEXT: s_cmp_lg_u32 s16, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
@@ -4934,25 +4852,25 @@ define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
;
; GFX9-LABEL: s_fshr_i128:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b64 s[10:11], 0x7f
+; GFX9-NEXT: s_movk_i32 s10, 0x7f
+; GFX9-NEXT: s_mov_b32 s11, 0
; GFX9-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX9-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
-; GFX9-NEXT: s_sub_i32 s9, 64, 1
-; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s9
-; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
+; GFX9-NEXT: s_lshl_b64 s[14:15], s[0:1], 1
+; GFX9-NEXT: s_lshr_b32 s10, s1, 31
+; GFX9-NEXT: s_lshl_b64 s[0:1], s[2:3], 1
+; GFX9-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1]
; GFX9-NEXT: s_sub_i32 s13, s8, 64
; GFX9-NEXT: s_sub_i32 s9, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64
; GFX9-NEXT: s_cselect_b32 s16, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b32 s17, 1, 0
-; GFX9-NEXT: s_lshl_b64 s[2:3], s[10:11], s8
-; GFX9-NEXT: s_lshr_b64 s[14:15], s[10:11], s9
+; GFX9-NEXT: s_lshl_b64 s[2:3], s[14:15], s8
+; GFX9-NEXT: s_lshr_b64 s[10:11], s[14:15], s9
; GFX9-NEXT: s_lshl_b64 s[8:9], s[0:1], s8
-; GFX9-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9]
-; GFX9-NEXT: s_lshl_b64 s[10:11], s[10:11], s13
+; GFX9-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
+; GFX9-NEXT: s_lshl_b64 s[10:11], s[14:15], s13
; GFX9-NEXT: s_cmp_lg_u32 s16, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
@@ -4981,12 +4899,12 @@ define amdgpu_ps i128 @s_fshr_i128(i128 inreg %lhs, i128 inreg %rhs, i128 inreg
;
; GFX10-LABEL: s_fshr_i128:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_mov_b64 s[10:11], 0x7f
+; GFX10-NEXT: s_movk_i32 s10, 0x7f
+; GFX10-NEXT: s_mov_b32 s11, 0
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
-; GFX10-NEXT: s_sub_i32 s13, 64, 1
; GFX10-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
-; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s13
+; GFX10-NEXT: s_lshr_b32 s10, s1, 31
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX10-NEXT: s_or_b64 s[2:3], s[10:11], s[2:3]
; GFX10-NEXT: s_sub_i32 s13, s8, 64
@@ -5036,29 +4954,27 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX6-NEXT: s_movk_i32 s4, 0x7f
; GFX6-NEXT: v_and_b32_e32 v14, s4, v8
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v8
-; GFX6-NEXT: v_and_b32_e32 v15, s4, v8
-; GFX6-NEXT: s_sub_i32 s4, 64, 1
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[0:1], s4
; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
-; GFX6-NEXT: v_or_b32_e32 v2, v8, v2
-; GFX6-NEXT: v_or_b32_e32 v3, v9, v3
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v15
-; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, 64, v15
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[0:1], v8
+; GFX6-NEXT: v_and_b32_e32 v15, s4, v8
+; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v1
+; GFX6-NEXT: v_or_b32_e32 v2, v0, v2
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, 64, v15
+; GFX6-NEXT: v_lshr_b64 v[0:1], v[8:9], v0
; GFX6-NEXT: v_lshl_b64 v[10:11], v[2:3], v15
-; GFX6-NEXT: v_lshl_b64 v[12:13], v[0:1], v15
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v16
-; GFX6-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, 64, v15
+; GFX6-NEXT: v_lshl_b64 v[12:13], v[8:9], v15
+; GFX6-NEXT: v_or_b32_e32 v10, v0, v10
+; GFX6-NEXT: v_or_b32_e32 v11, v1, v11
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[8:9], v16
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
-; GFX6-NEXT: v_or_b32_e32 v9, v9, v11
-; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15
-; GFX6-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v10, v0, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v11, v1, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 64, v14
; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], v14
; GFX6-NEXT: v_lshl_b64 v[2:3], v[6:7], v2
@@ -5075,10 +4991,10 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
-; GFX6-NEXT: v_or_b32_e32 v0, v10, v0
-; GFX6-NEXT: v_or_b32_e32 v1, v11, v1
-; GFX6-NEXT: v_or_b32_e32 v2, v12, v2
-; GFX6-NEXT: v_or_b32_e32 v3, v13, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v12, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v13, v1
+; GFX6-NEXT: v_or_b32_e32 v2, v10, v2
+; GFX6-NEXT: v_or_b32_e32 v3, v11, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fshr_i128:
@@ -5087,29 +5003,27 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX8-NEXT: s_movk_i32 s4, 0x7f
; GFX8-NEXT: v_and_b32_e32 v14, s4, v8
; GFX8-NEXT: v_xor_b32_e32 v8, -1, v8
-; GFX8-NEXT: v_and_b32_e32 v15, s4, v8
-; GFX8-NEXT: s_sub_i32 s4, 64, 1
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], s4, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX8-NEXT: v_or_b32_e32 v2, v8, v2
-; GFX8-NEXT: v_or_b32_e32 v3, v9, v3
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v15
-; GFX8-NEXT: v_subrev_u32_e32 v16, vcc, 64, v15
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], v8, v[0:1]
+; GFX8-NEXT: v_and_b32_e32 v15, s4, v8
+; GFX8-NEXT: v_lshlrev_b64 v[8:9], 1, v[0:1]
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 31, v1
+; GFX8-NEXT: v_or_b32_e32 v2, v0, v2
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, 64, v15
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, v[8:9]
; GFX8-NEXT: v_lshlrev_b64 v[10:11], v15, v[2:3]
-; GFX8-NEXT: v_lshlrev_b64 v[12:13], v15, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v16, v[0:1]
-; GFX8-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX8-NEXT: v_subrev_u32_e32 v16, vcc, 64, v15
+; GFX8-NEXT: v_lshlrev_b64 v[12:13], v15, v[8:9]
+; GFX8-NEXT: v_or_b32_e32 v10, v0, v10
+; GFX8-NEXT: v_or_b32_e32 v11, v1, v11
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v16, v[8:9]
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
-; GFX8-NEXT: v_or_b32_e32 v9, v9, v11
-; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15
-; GFX8-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v0, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v1, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 64, v14
; GFX8-NEXT: v_lshrrev_b64 v[0:1], v14, v[4:5]
; GFX8-NEXT: v_lshlrev_b64 v[2:3], v2, v[6:7]
@@ -5126,10 +5040,10 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
-; GFX8-NEXT: v_or_b32_e32 v0, v10, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v11, v1
-; GFX8-NEXT: v_or_b32_e32 v2, v12, v2
-; GFX8-NEXT: v_or_b32_e32 v3, v13, v3
+; GFX8-NEXT: v_or_b32_e32 v0, v12, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v13, v1
+; GFX8-NEXT: v_or_b32_e32 v2, v10, v2
+; GFX8-NEXT: v_or_b32_e32 v3, v11, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_i128:
@@ -5138,30 +5052,28 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX9-NEXT: s_movk_i32 s4, 0x7f
; GFX9-NEXT: v_and_b32_e32 v14, s4, v8
; GFX9-NEXT: v_xor_b32_e32 v8, -1, v8
-; GFX9-NEXT: v_and_b32_e32 v15, s4, v8
-; GFX9-NEXT: s_sub_i32 s4, 64, 1
-; GFX9-NEXT: v_lshrrev_b64 v[8:9], s4, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX9-NEXT: v_or_b32_e32 v2, v8, v2
-; GFX9-NEXT: v_or_b32_e32 v3, v9, v3
-; GFX9-NEXT: v_sub_u32_e32 v8, 64, v15
-; GFX9-NEXT: v_subrev_u32_e32 v16, 64, v15
-; GFX9-NEXT: v_lshrrev_b64 v[8:9], v8, v[0:1]
+; GFX9-NEXT: v_and_b32_e32 v15, s4, v8
+; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[0:1]
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 31, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v0, v2
+; GFX9-NEXT: v_sub_u32_e32 v0, 64, v15
+; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, v[8:9]
; GFX9-NEXT: v_lshlrev_b64 v[10:11], v15, v[2:3]
-; GFX9-NEXT: v_lshlrev_b64 v[12:13], v15, v[0:1]
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], v16, v[0:1]
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX9-NEXT: v_subrev_u32_e32 v16, 64, v15
+; GFX9-NEXT: v_lshlrev_b64 v[12:13], v15, v[8:9]
+; GFX9-NEXT: v_or_b32_e32 v10, v0, v10
+; GFX9-NEXT: v_or_b32_e32 v11, v1, v11
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], v16, v[8:9]
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v15
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
-; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v12, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v13, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v15
-; GFX9-NEXT: v_cndmask_b32_e32 v12, v0, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v10, v0, v2, vcc
; GFX9-NEXT: v_sub_u32_e32 v2, 64, v14
-; GFX9-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v1, v3, vcc
; GFX9-NEXT: v_lshrrev_b64 v[0:1], v14, v[4:5]
; GFX9-NEXT: v_lshlrev_b64 v[2:3], v2, v[6:7]
; GFX9-NEXT: v_subrev_u32_e32 v15, 64, v14
@@ -5177,59 +5089,57 @@ define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, 0, v9, vcc
-; GFX9-NEXT: v_or_b32_e32 v0, v10, v0
-; GFX9-NEXT: v_or_b32_e32 v1, v11, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v12, v2
-; GFX9-NEXT: v_or_b32_e32 v3, v13, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v12, v0
+; GFX9-NEXT: v_or_b32_e32 v1, v13, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v10, v2
+; GFX9-NEXT: v_or_b32_e32 v3, v11, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fshr_i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v11, -1, v8
-; GFX10-NEXT: s_sub_i32 s4, 64, 1
-; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX10-NEXT: v_lshrrev_b64 v[9:10], s4, v[0:1]
+; GFX10-NEXT: v_xor_b32_e32 v9, -1, v8
; GFX10-NEXT: s_movk_i32 s4, 0x7f
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX10-NEXT: v_and_b32_e32 v18, s4, v11
+; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX10-NEXT: v_lshrrev_b32_e32 v10, 31, v1
; GFX10-NEXT: v_and_b32_e32 v19, s4, v8
-; GFX10-NEXT: v_or_b32_e32 v3, v10, v3
-; GFX10-NEXT: v_or_b32_e32 v2, v9, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v18
+; GFX10-NEXT: v_and_b32_e32 v18, s4, v9
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX10-NEXT: v_or_b32_e32 v2, v10, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v16, 64, v19
-; GFX10-NEXT: v_subrev_nc_u32_e32 v20, 64, v18
-; GFX10-NEXT: v_lshrrev_b64 v[14:15], v19, v[4:5]
+; GFX10-NEXT: v_sub_nc_u32_e32 v10, 64, v18
+; GFX10-NEXT: v_subrev_nc_u32_e32 v21, 64, v18
+; GFX10-NEXT: v_subrev_nc_u32_e32 v20, 64, v19
; GFX10-NEXT: v_lshlrev_b64 v[8:9], v18, v[2:3]
+; GFX10-NEXT: v_lshrrev_b64 v[12:13], v19, v[4:5]
; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[16:17], v16, v[6:7]
-; GFX10-NEXT: v_lshlrev_b64 v[12:13], v18, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v20, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[14:15], v18, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], v21, v[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v18
; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v19
; GFX10-NEXT: v_or_b32_e32 v10, v10, v8
-; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v19
; GFX10-NEXT: v_or_b32_e32 v11, v11, v9
-; GFX10-NEXT: v_or_b32_e32 v14, v14, v16
-; GFX10-NEXT: v_or_b32_e32 v15, v15, v17
+; GFX10-NEXT: v_lshrrev_b64 v[8:9], v20, v[6:7]
+; GFX10-NEXT: v_or_b32_e32 v12, v12, v16
+; GFX10-NEXT: v_or_b32_e32 v13, v13, v17
; GFX10-NEXT: v_cndmask_b32_e32 v10, v0, v10, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[8:9], v8, v[6:7]
; GFX10-NEXT: v_cndmask_b32_e32 v11, v1, v11, vcc_lo
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v19, v[6:7]
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v18
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v12, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 0, v19
-; GFX10-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v14, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v9, v15, s4
-; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v13, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v9, v13, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v15, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, v2, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, v3, s6
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s5
; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, v5, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, v1, s4
-; GFX10-NEXT: v_or_b32_e32 v0, v12, v4
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, v3, s6
+; GFX10-NEXT: v_or_b32_e32 v0, v14, v4
; GFX10-NEXT: v_or_b32_e32 v1, v7, v5
; GFX10-NEXT: v_or_b32_e32 v2, v2, v6
; GFX10-NEXT: v_or_b32_e32 v3, v3, v8
@@ -5244,20 +5154,20 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX6-NEXT: s_movk_i32 s8, 0x7f
; GFX6-NEXT: v_and_b32_e32 v6, s8, v0
; GFX6-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX6-NEXT: s_sub_i32 s10, 64, 1
; GFX6-NEXT: v_and_b32_e32 v7, s8, v0
-; GFX6-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s10
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
+; GFX6-NEXT: s_lshr_b32 s8, s1, 31
+; GFX6-NEXT: s_mov_b32 s9, 0
+; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], 1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, 64, v7
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
-; GFX6-NEXT: v_lshr_b64 v[0:1], s[8:9], v0
+; GFX6-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
+; GFX6-NEXT: v_lshr_b64 v[0:1], s[10:11], v0
; GFX6-NEXT: v_lshl_b64 v[2:3], s[0:1], v7
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, 64, v7
-; GFX6-NEXT: v_lshl_b64 v[4:5], s[8:9], v7
+; GFX6-NEXT: v_lshl_b64 v[4:5], s[10:11], v7
; GFX6-NEXT: v_or_b32_e32 v2, v0, v2
; GFX6-NEXT: v_or_b32_e32 v3, v1, v3
-; GFX6-NEXT: v_lshl_b64 v[0:1], s[8:9], v8
+; GFX6-NEXT: v_lshl_b64 v[0:1], s[10:11], v8
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
@@ -5297,20 +5207,20 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX8-NEXT: s_movk_i32 s8, 0x7f
; GFX8-NEXT: v_and_b32_e32 v6, s8, v0
; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX8-NEXT: s_sub_i32 s10, 64, 1
; GFX8-NEXT: v_and_b32_e32 v7, s8, v0
-; GFX8-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s10
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
+; GFX8-NEXT: s_lshr_b32 s8, s1, 31
+; GFX8-NEXT: s_mov_b32 s9, 0
+; GFX8-NEXT: s_lshl_b64 s[0:1], s[2:3], 1
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, 64, v7
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
-; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[8:9]
+; GFX8-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[10:11]
; GFX8-NEXT: v_lshlrev_b64 v[2:3], v7, s[0:1]
; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, 64, v7
-; GFX8-NEXT: v_lshlrev_b64 v[4:5], v7, s[8:9]
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v7, s[10:11]
; GFX8-NEXT: v_or_b32_e32 v2, v0, v2
; GFX8-NEXT: v_or_b32_e32 v3, v1, v3
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, s[8:9]
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, s[10:11]
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
@@ -5350,20 +5260,20 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX9-NEXT: s_movk_i32 s8, 0x7f
; GFX9-NEXT: v_and_b32_e32 v6, s8, v0
; GFX9-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX9-NEXT: s_sub_i32 s10, 64, 1
; GFX9-NEXT: v_and_b32_e32 v7, s8, v0
-; GFX9-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s10
-; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
+; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
+; GFX9-NEXT: s_lshr_b32 s8, s1, 31
+; GFX9-NEXT: s_mov_b32 s9, 0
+; GFX9-NEXT: s_lshl_b64 s[0:1], s[2:3], 1
; GFX9-NEXT: v_sub_u32_e32 v0, 64, v7
-; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
-; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[8:9]
+; GFX9-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
+; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[10:11]
; GFX9-NEXT: v_lshlrev_b64 v[2:3], v7, s[0:1]
; GFX9-NEXT: v_subrev_u32_e32 v8, 64, v7
-; GFX9-NEXT: v_lshlrev_b64 v[4:5], v7, s[8:9]
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], v7, s[10:11]
; GFX9-NEXT: v_or_b32_e32 v2, v0, v2
; GFX9-NEXT: v_or_b32_e32 v3, v1, v3
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, s[8:9]
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, s[10:11]
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v7
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
@@ -5402,9 +5312,9 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
; GFX10: ; %bb.0:
; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0
; GFX10-NEXT: s_movk_i32 s10, 0x7f
-; GFX10-NEXT: s_sub_i32 s8, 64, 1
+; GFX10-NEXT: s_lshr_b32 s8, s1, 31
; GFX10-NEXT: v_and_b32_e32 v13, s10, v0
-; GFX10-NEXT: s_lshr_b64 s[8:9], s[0:1], s8
+; GFX10-NEXT: s_mov_b32 s9, 0
; GFX10-NEXT: v_and_b32_e32 v12, s10, v1
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
@@ -5454,25 +5364,25 @@ define amdgpu_ps <4 x float> @v_fshr_i128_ssv(i128 inreg %lhs, i128 inreg %rhs,
define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 inreg %amt) {
; GFX6-LABEL: v_fshr_i128_svs:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b64 s[6:7], 0x7f
+; GFX6-NEXT: s_movk_i32 s6, 0x7f
+; GFX6-NEXT: s_mov_b32 s7, 0
; GFX6-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX6-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
-; GFX6-NEXT: s_sub_i32 s5, 64, 1
-; GFX6-NEXT: s_lshl_b64 s[6:7], s[0:1], 1
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s5
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
+; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
+; GFX6-NEXT: s_lshr_b32 s6, s1, 31
+; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], 1
+; GFX6-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1]
; GFX6-NEXT: s_sub_i32 s9, s4, 64
; GFX6-NEXT: s_sub_i32 s5, 64, s4
; GFX6-NEXT: s_cmp_lt_u32 s4, 64
; GFX6-NEXT: s_cselect_b32 s12, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s4, 0
; GFX6-NEXT: s_cselect_b32 s13, 1, 0
-; GFX6-NEXT: s_lshl_b64 s[2:3], s[6:7], s4
-; GFX6-NEXT: s_lshr_b64 s[10:11], s[6:7], s5
+; GFX6-NEXT: s_lshl_b64 s[2:3], s[10:11], s4
+; GFX6-NEXT: s_lshr_b64 s[6:7], s[10:11], s5
; GFX6-NEXT: s_lshl_b64 s[4:5], s[0:1], s4
-; GFX6-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
-; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], s9
+; GFX6-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
+; GFX6-NEXT: s_lshl_b64 s[6:7], s[10:11], s9
; GFX6-NEXT: s_cmp_lg_u32 s12, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
@@ -5510,25 +5420,25 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
;
; GFX8-LABEL: v_fshr_i128_svs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_mov_b64 s[6:7], 0x7f
+; GFX8-NEXT: s_movk_i32 s6, 0x7f
+; GFX8-NEXT: s_mov_b32 s7, 0
; GFX8-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX8-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
-; GFX8-NEXT: s_sub_i32 s5, 64, 1
-; GFX8-NEXT: s_lshl_b64 s[6:7], s[0:1], 1
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s5
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
+; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
+; GFX8-NEXT: s_lshr_b32 s6, s1, 31
+; GFX8-NEXT: s_lshl_b64 s[0:1], s[2:3], 1
+; GFX8-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1]
; GFX8-NEXT: s_sub_i32 s9, s4, 64
; GFX8-NEXT: s_sub_i32 s5, 64, s4
; GFX8-NEXT: s_cmp_lt_u32 s4, 64
; GFX8-NEXT: s_cselect_b32 s12, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s4, 0
; GFX8-NEXT: s_cselect_b32 s13, 1, 0
-; GFX8-NEXT: s_lshl_b64 s[2:3], s[6:7], s4
-; GFX8-NEXT: s_lshr_b64 s[10:11], s[6:7], s5
+; GFX8-NEXT: s_lshl_b64 s[2:3], s[10:11], s4
+; GFX8-NEXT: s_lshr_b64 s[6:7], s[10:11], s5
; GFX8-NEXT: s_lshl_b64 s[4:5], s[0:1], s4
-; GFX8-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
-; GFX8-NEXT: s_lshl_b64 s[6:7], s[6:7], s9
+; GFX8-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
+; GFX8-NEXT: s_lshl_b64 s[6:7], s[10:11], s9
; GFX8-NEXT: s_cmp_lg_u32 s12, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
@@ -5566,25 +5476,25 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
;
; GFX9-LABEL: v_fshr_i128_svs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
+; GFX9-NEXT: s_movk_i32 s6, 0x7f
+; GFX9-NEXT: s_mov_b32 s7, 0
; GFX9-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX9-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
-; GFX9-NEXT: s_sub_i32 s5, 64, 1
-; GFX9-NEXT: s_lshl_b64 s[6:7], s[0:1], 1
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s5
-; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
+; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
+; GFX9-NEXT: s_lshr_b32 s6, s1, 31
+; GFX9-NEXT: s_lshl_b64 s[0:1], s[2:3], 1
+; GFX9-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1]
; GFX9-NEXT: s_sub_i32 s9, s4, 64
; GFX9-NEXT: s_sub_i32 s5, 64, s4
; GFX9-NEXT: s_cmp_lt_u32 s4, 64
; GFX9-NEXT: s_cselect_b32 s12, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s4, 0
; GFX9-NEXT: s_cselect_b32 s13, 1, 0
-; GFX9-NEXT: s_lshl_b64 s[2:3], s[6:7], s4
-; GFX9-NEXT: s_lshr_b64 s[10:11], s[6:7], s5
+; GFX9-NEXT: s_lshl_b64 s[2:3], s[10:11], s4
+; GFX9-NEXT: s_lshr_b64 s[6:7], s[10:11], s5
; GFX9-NEXT: s_lshl_b64 s[4:5], s[0:1], s4
-; GFX9-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
-; GFX9-NEXT: s_lshl_b64 s[6:7], s[6:7], s9
+; GFX9-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
+; GFX9-NEXT: s_lshl_b64 s[6:7], s[10:11], s9
; GFX9-NEXT: s_cmp_lg_u32 s12, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
@@ -5622,12 +5532,12 @@ define amdgpu_ps <4 x float> @v_fshr_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
;
; GFX10-LABEL: v_fshr_i128_svs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f
+; GFX10-NEXT: s_movk_i32 s6, 0x7f
+; GFX10-NEXT: s_mov_b32 s7, 0
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
-; GFX10-NEXT: s_sub_i32 s9, 64, 1
; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
-; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s9
+; GFX10-NEXT: s_lshr_b32 s6, s1, 31
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX10-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3]
; GFX10-NEXT: s_sub_i32 s9, s4, 64
@@ -5684,37 +5594,35 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX6-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX6-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX6-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
-; GFX6-NEXT: s_sub_i32 s5, 64, 1
-; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s5
; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GFX6-NEXT: s_sub_i32 s5, s4, 64
; GFX6-NEXT: s_sub_i32 s6, 64, s4
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
+; GFX6-NEXT: v_lshl_b64 v[4:5], v[0:1], 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v1
; GFX6-NEXT: s_cmp_lt_u32 s4, 64
+; GFX6-NEXT: v_or_b32_e32 v2, v0, v2
; GFX6-NEXT: s_cselect_b32 s7, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s4, 0
-; GFX6-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX6-NEXT: v_or_b32_e32 v3, v5, v3
; GFX6-NEXT: s_cselect_b32 s9, 1, 0
+; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s6
; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s4
-; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], s4
+; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], s4
; GFX6-NEXT: s_and_b32 s4, 1, s7
-; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s6
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX6-NEXT: s_and_b32 s4, 1, s9
; GFX6-NEXT: s_sub_i32 s10, s8, 64
; GFX6-NEXT: s_sub_i32 s9, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64
-; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s5
-; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX6-NEXT: v_or_b32_e32 v6, v0, v6
+; GFX6-NEXT: v_or_b32_e32 v7, v1, v7
+; GFX6-NEXT: v_lshl_b64 v[0:1], v[4:5], s5
; GFX6-NEXT: s_cselect_b32 s11, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b32 s12, 1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX6-NEXT: s_lshr_b64 s[4:5], s[2:3], s8
; GFX6-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
@@ -5729,8 +5637,8 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX6-NEXT: s_cselect_b64 s[2:3], s[4:5], 0
-; GFX6-NEXT: v_or_b32_e32 v0, s0, v6
-; GFX6-NEXT: v_or_b32_e32 v1, s1, v7
+; GFX6-NEXT: v_or_b32_e32 v0, s0, v4
+; GFX6-NEXT: v_or_b32_e32 v1, s1, v5
; GFX6-NEXT: v_or_b32_e32 v2, s2, v2
; GFX6-NEXT: v_or_b32_e32 v3, s3, v3
; GFX6-NEXT: ; return to shader part epilog
@@ -5740,37 +5648,35 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX8-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX8-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX8-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
-; GFX8-NEXT: s_sub_i32 s5, 64, 1
-; GFX8-NEXT: v_lshrrev_b64 v[4:5], s5, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX8-NEXT: s_sub_i32 s5, s4, 64
; GFX8-NEXT: s_sub_i32 s6, 64, s4
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], 1, v[0:1]
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 31, v1
; GFX8-NEXT: s_cmp_lt_u32 s4, 64
+; GFX8-NEXT: v_or_b32_e32 v2, v0, v2
; GFX8-NEXT: s_cselect_b32 s7, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s4, 0
-; GFX8-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: s_cselect_b32 s9, 1, 0
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], s6, v[4:5]
; GFX8-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3]
-; GFX8-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[8:9], s4, v[4:5]
; GFX8-NEXT: s_and_b32 s4, 1, s7
-; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: s_and_b32 s4, 1, s9
; GFX8-NEXT: s_sub_i32 s10, s8, 64
; GFX8-NEXT: s_sub_i32 s9, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
-; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX8-NEXT: v_or_b32_e32 v6, v0, v6
+; GFX8-NEXT: v_or_b32_e32 v7, v1, v7
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[4:5]
; GFX8-NEXT: s_cselect_b32 s11, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b32 s12, 1, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: s_lshr_b64 s[4:5], s[2:3], s8
; GFX8-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
@@ -5785,8 +5691,8 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX8-NEXT: s_cselect_b64 s[2:3], s[4:5], 0
-; GFX8-NEXT: v_or_b32_e32 v0, s0, v6
-; GFX8-NEXT: v_or_b32_e32 v1, s1, v7
+; GFX8-NEXT: v_or_b32_e32 v0, s0, v4
+; GFX8-NEXT: v_or_b32_e32 v1, s1, v5
; GFX8-NEXT: v_or_b32_e32 v2, s2, v2
; GFX8-NEXT: v_or_b32_e32 v3, s3, v3
; GFX8-NEXT: ; return to shader part epilog
@@ -5796,37 +5702,35 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX9-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
-; GFX9-NEXT: s_sub_i32 s5, 64, 1
-; GFX9-NEXT: v_lshrrev_b64 v[4:5], s5, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
; GFX9-NEXT: s_sub_i32 s5, s4, 64
; GFX9-NEXT: s_sub_i32 s6, 64, s4
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], 1, v[0:1]
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 31, v1
; GFX9-NEXT: s_cmp_lt_u32 s4, 64
+; GFX9-NEXT: v_or_b32_e32 v2, v0, v2
; GFX9-NEXT: s_cselect_b32 s7, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s4, 0
-; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX9-NEXT: v_or_b32_e32 v3, v5, v3
; GFX9-NEXT: s_cselect_b32 s9, 1, 0
+; GFX9-NEXT: v_lshrrev_b64 v[0:1], s6, v[4:5]
; GFX9-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3]
-; GFX9-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1]
+; GFX9-NEXT: v_lshlrev_b64 v[8:9], s4, v[4:5]
; GFX9-NEXT: s_and_b32 s4, 1, s7
-; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: s_and_b32 s4, 1, s9
; GFX9-NEXT: s_sub_i32 s10, s8, 64
; GFX9-NEXT: s_sub_i32 s9, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_or_b32_e32 v6, v0, v6
+; GFX9-NEXT: v_or_b32_e32 v7, v1, v7
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[4:5]
; GFX9-NEXT: s_cselect_b32 s11, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b32 s12, 1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: s_lshr_b64 s[4:5], s[2:3], s8
; GFX9-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
@@ -5841,29 +5745,27 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX9-NEXT: s_cselect_b64 s[2:3], s[4:5], 0
-; GFX9-NEXT: v_or_b32_e32 v0, s0, v6
-; GFX9-NEXT: v_or_b32_e32 v1, s1, v7
+; GFX9-NEXT: v_or_b32_e32 v0, s0, v4
+; GFX9-NEXT: v_or_b32_e32 v1, s1, v5
; GFX9-NEXT: v_or_b32_e32 v2, s2, v2
; GFX9-NEXT: v_or_b32_e32 v3, s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_fshr_i128_vss:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_i32 s6, 64, 1
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX10-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
+; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v1
; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX10-NEXT: s_andn2_b64 s[8:9], s[6:7], s[4:5]
; GFX10-NEXT: s_and_b64 s[6:7], s[4:5], s[6:7]
-; GFX10-NEXT: s_sub_i32 s4, 64, s8
; GFX10-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX10-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX10-NEXT: s_sub_i32 s4, 64, s8
; GFX10-NEXT: s_sub_i32 s5, s8, 64
; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
-; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0
; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3]
+; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1]
; GFX10-NEXT: s_cselect_b32 s7, 1, 0
@@ -5910,55 +5812,47 @@ define amdgpu_ps <4 x float> @v_fshr_i128_vss(i128 %lhs, i128 inreg %rhs, i128 i
define amdgpu_ps i128 @s_fshr_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-LABEL: s_fshr_i128_65:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_sub_i32 s3, 64, 63
; GFX6-NEXT: s_mov_b32 s4, 0
; GFX6-NEXT: s_lshl_b32 s5, s0, 31
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s3
; GFX6-NEXT: s_lshl_b32 s3, s2, 31
+; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX6-NEXT: s_mov_b32 s2, s4
; GFX6-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
-; GFX6-NEXT: s_sub_i32 s0, 0x41, 64
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
+; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
; GFX6-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fshr_i128_65:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_sub_i32 s3, 64, 63
; GFX8-NEXT: s_mov_b32 s4, 0
; GFX8-NEXT: s_lshl_b32 s5, s0, 31
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s3
; GFX8-NEXT: s_lshl_b32 s3, s2, 31
+; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX8-NEXT: s_mov_b32 s2, s4
; GFX8-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
-; GFX8-NEXT: s_sub_i32 s0, 0x41, 64
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
+; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
; GFX8-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fshr_i128_65:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sub_i32 s3, 64, 63
; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: s_lshl_b32 s5, s0, 31
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s3
; GFX9-NEXT: s_lshl_b32 s3, s2, 31
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX9-NEXT: s_mov_b32 s2, s4
; GFX9-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
-; GFX9-NEXT: s_sub_i32 s0, 0x41, 64
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
+; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
; GFX9-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_fshr_i128_65:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sub_i32 s3, 64, 63
-; GFX10-NEXT: s_lshl_b32 s5, s0, 31
-; GFX10-NEXT: s_lshr_b64 s[8:9], s[0:1], s3
-; GFX10-NEXT: s_sub_i32 s0, 0x41, 64
; GFX10-NEXT: s_mov_b32 s4, 0
-; GFX10-NEXT: s_lshr_b64 s[0:1], s[6:7], s0
; GFX10-NEXT: s_lshl_b32 s3, s2, 31
+; GFX10-NEXT: s_lshl_b32 s5, s0, 31
+; GFX10-NEXT: s_lshr_b64 s[8:9], s[0:1], 1
+; GFX10-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
; GFX10-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
@@ -5971,12 +5865,10 @@ define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) {
; GFX6-LABEL: v_fshr_i128_65:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_sub_i32 s4, 64, 63
; GFX6-NEXT: v_mov_b32_e32 v4, v2
-; GFX6-NEXT: v_lshr_b64 v[2:3], v[0:1], s4
-; GFX6-NEXT: s_sub_i32 s4, 0x41, 64
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 31, v0
-; GFX6-NEXT: v_lshr_b64 v[0:1], v[6:7], s4
+; GFX6-NEXT: v_lshr_b64 v[2:3], v[0:1], 1
+; GFX6-NEXT: v_lshr_b64 v[0:1], v[6:7], 1
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 31, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: v_or_b32_e32 v1, v5, v1
@@ -5985,12 +5877,10 @@ define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) {
; GFX8-LABEL: v_fshr_i128_65:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_sub_i32 s4, 64, 63
; GFX8-NEXT: v_mov_b32_e32 v4, v2
-; GFX8-NEXT: v_lshrrev_b64 v[2:3], s4, v[0:1]
-; GFX8-NEXT: s_sub_i32 s4, 0x41, 64
; GFX8-NEXT: v_lshlrev_b32_e32 v5, 31, v0
-; GFX8-NEXT: v_lshrrev_b64 v[0:1], s4, v[6:7]
+; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1]
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[6:7]
; GFX8-NEXT: v_lshlrev_b32_e32 v4, 31, v4
; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
; GFX8-NEXT: v_or_b32_e32 v1, v5, v1
@@ -5999,12 +5889,10 @@ define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) {
; GFX9-LABEL: v_fshr_i128_65:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_sub_i32 s4, 64, 63
; GFX9-NEXT: v_mov_b32_e32 v4, v2
-; GFX9-NEXT: v_lshrrev_b64 v[2:3], s4, v[0:1]
-; GFX9-NEXT: s_sub_i32 s4, 0x41, 64
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 31, v0
-; GFX9-NEXT: v_lshrrev_b64 v[0:1], s4, v[6:7]
+; GFX9-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1]
+; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[6:7]
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 31, v4
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_or_b32_e32 v1, v5, v1
@@ -6015,10 +5903,8 @@ define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v8, v2
-; GFX10-NEXT: s_sub_i32 s4, 64, 63
-; GFX10-NEXT: s_sub_i32 s5, 0x41, 64
-; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[0:1]
-; GFX10-NEXT: v_lshrrev_b64 v[4:5], s5, v[6:7]
+; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7]
+; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1]
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 31, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 31, v8
; GFX10-NEXT: v_or_b32_e32 v1, v9, v5
@@ -6032,36 +5918,37 @@ define i128 @v_fshr_i128_65(i128 %lhs, i128 %rhs) {
define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs, <2 x i128> inreg %amt) {
; GFX6-LABEL: s_fshr_v2i128:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_mov_b64 s[18:19], 0x7f
-; GFX6-NEXT: s_sub_i32 s28, 64, 1
+; GFX6-NEXT: s_movk_i32 s18, 0x7f
+; GFX6-NEXT: s_mov_b32 s19, 0
; GFX6-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX6-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX6-NEXT: s_lshl_b64 s[24:25], s[0:1], 1
-; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], s28
+; GFX6-NEXT: s_lshr_b32 s0, s1, 31
+; GFX6-NEXT: s_mov_b32 s1, s19
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX6-NEXT: s_sub_i32 s23, s16, 64
; GFX6-NEXT: s_sub_i32 s17, 64, s16
; GFX6-NEXT: s_cmp_lt_u32 s16, 64
-; GFX6-NEXT: s_cselect_b32 s29, 1, 0
+; GFX6-NEXT: s_cselect_b32 s28, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s16, 0
-; GFX6-NEXT: s_cselect_b32 s30, 1, 0
+; GFX6-NEXT: s_cselect_b32 s29, 1, 0
; GFX6-NEXT: s_lshl_b64 s[2:3], s[24:25], s16
; GFX6-NEXT: s_lshr_b64 s[26:27], s[24:25], s17
; GFX6-NEXT: s_lshl_b64 s[16:17], s[0:1], s16
; GFX6-NEXT: s_or_b64 s[16:17], s[26:27], s[16:17]
; GFX6-NEXT: s_lshl_b64 s[24:25], s[24:25], s23
-; GFX6-NEXT: s_cmp_lg_u32 s29, 0
+; GFX6-NEXT: s_cmp_lg_u32 s28, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX6-NEXT: s_cselect_b64 s[16:17], s[16:17], s[24:25]
-; GFX6-NEXT: s_cmp_lg_u32 s30, 0
+; GFX6-NEXT: s_cmp_lg_u32 s29, 0
; GFX6-NEXT: s_cselect_b64 s[16:17], s[0:1], s[16:17]
; GFX6-NEXT: s_sub_i32 s26, s22, 64
; GFX6-NEXT: s_sub_i32 s24, 64, s22
; GFX6-NEXT: s_cmp_lt_u32 s22, 64
; GFX6-NEXT: s_cselect_b32 s27, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s22, 0
-; GFX6-NEXT: s_cselect_b32 s29, 1, 0
+; GFX6-NEXT: s_cselect_b32 s28, 1, 0
; GFX6-NEXT: s_lshr_b64 s[0:1], s[10:11], s22
; GFX6-NEXT: s_lshl_b64 s[24:25], s[10:11], s24
; GFX6-NEXT: s_lshr_b64 s[22:23], s[8:9], s22
@@ -6069,7 +5956,7 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX6-NEXT: s_lshr_b64 s[10:11], s[10:11], s26
; GFX6-NEXT: s_cmp_lg_u32 s27, 0
; GFX6-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11]
-; GFX6-NEXT: s_cmp_lg_u32 s29, 0
+; GFX6-NEXT: s_cmp_lg_u32 s28, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
; GFX6-NEXT: s_cmp_lg_u32 s27, 0
; GFX6-NEXT: s_cselect_b64 s[10:11], s[0:1], 0
@@ -6078,9 +5965,9 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX6-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX6-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX6-NEXT: s_lshl_b64 s[16:17], s[4:5], 1
-; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], s28
-; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
-; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
+; GFX6-NEXT: s_lshr_b32 s18, s5, 31
+; GFX6-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
+; GFX6-NEXT: s_or_b64 s[4:5], s[18:19], s[4:5]
; GFX6-NEXT: s_sub_i32 s9, s10, 64
; GFX6-NEXT: s_sub_i32 s11, 64, s10
; GFX6-NEXT: s_cmp_lt_u32 s10, 64
@@ -6120,36 +6007,37 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
;
; GFX8-LABEL: s_fshr_v2i128:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_mov_b64 s[18:19], 0x7f
-; GFX8-NEXT: s_sub_i32 s28, 64, 1
+; GFX8-NEXT: s_movk_i32 s18, 0x7f
+; GFX8-NEXT: s_mov_b32 s19, 0
; GFX8-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX8-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX8-NEXT: s_lshl_b64 s[24:25], s[0:1], 1
-; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], s28
+; GFX8-NEXT: s_lshr_b32 s0, s1, 31
+; GFX8-NEXT: s_mov_b32 s1, s19
; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX8-NEXT: s_sub_i32 s23, s16, 64
; GFX8-NEXT: s_sub_i32 s17, 64, s16
; GFX8-NEXT: s_cmp_lt_u32 s16, 64
-; GFX8-NEXT: s_cselect_b32 s29, 1, 0
+; GFX8-NEXT: s_cselect_b32 s28, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s16, 0
-; GFX8-NEXT: s_cselect_b32 s30, 1, 0
+; GFX8-NEXT: s_cselect_b32 s29, 1, 0
; GFX8-NEXT: s_lshl_b64 s[2:3], s[24:25], s16
; GFX8-NEXT: s_lshr_b64 s[26:27], s[24:25], s17
; GFX8-NEXT: s_lshl_b64 s[16:17], s[0:1], s16
; GFX8-NEXT: s_or_b64 s[16:17], s[26:27], s[16:17]
; GFX8-NEXT: s_lshl_b64 s[24:25], s[24:25], s23
-; GFX8-NEXT: s_cmp_lg_u32 s29, 0
+; GFX8-NEXT: s_cmp_lg_u32 s28, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX8-NEXT: s_cselect_b64 s[16:17], s[16:17], s[24:25]
-; GFX8-NEXT: s_cmp_lg_u32 s30, 0
+; GFX8-NEXT: s_cmp_lg_u32 s29, 0
; GFX8-NEXT: s_cselect_b64 s[16:17], s[0:1], s[16:17]
; GFX8-NEXT: s_sub_i32 s26, s22, 64
; GFX8-NEXT: s_sub_i32 s24, 64, s22
; GFX8-NEXT: s_cmp_lt_u32 s22, 64
; GFX8-NEXT: s_cselect_b32 s27, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s22, 0
-; GFX8-NEXT: s_cselect_b32 s29, 1, 0
+; GFX8-NEXT: s_cselect_b32 s28, 1, 0
; GFX8-NEXT: s_lshr_b64 s[0:1], s[10:11], s22
; GFX8-NEXT: s_lshl_b64 s[24:25], s[10:11], s24
; GFX8-NEXT: s_lshr_b64 s[22:23], s[8:9], s22
@@ -6157,7 +6045,7 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX8-NEXT: s_lshr_b64 s[10:11], s[10:11], s26
; GFX8-NEXT: s_cmp_lg_u32 s27, 0
; GFX8-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11]
-; GFX8-NEXT: s_cmp_lg_u32 s29, 0
+; GFX8-NEXT: s_cmp_lg_u32 s28, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
; GFX8-NEXT: s_cmp_lg_u32 s27, 0
; GFX8-NEXT: s_cselect_b64 s[10:11], s[0:1], 0
@@ -6166,9 +6054,9 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX8-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX8-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX8-NEXT: s_lshl_b64 s[16:17], s[4:5], 1
-; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], s28
-; GFX8-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
-; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
+; GFX8-NEXT: s_lshr_b32 s18, s5, 31
+; GFX8-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
+; GFX8-NEXT: s_or_b64 s[4:5], s[18:19], s[4:5]
; GFX8-NEXT: s_sub_i32 s9, s10, 64
; GFX8-NEXT: s_sub_i32 s11, 64, s10
; GFX8-NEXT: s_cmp_lt_u32 s10, 64
@@ -6208,36 +6096,37 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
;
; GFX9-LABEL: s_fshr_v2i128:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b64 s[18:19], 0x7f
-; GFX9-NEXT: s_sub_i32 s28, 64, 1
+; GFX9-NEXT: s_movk_i32 s18, 0x7f
+; GFX9-NEXT: s_mov_b32 s19, 0
; GFX9-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX9-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX9-NEXT: s_lshl_b64 s[24:25], s[0:1], 1
-; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s28
+; GFX9-NEXT: s_lshr_b32 s0, s1, 31
+; GFX9-NEXT: s_mov_b32 s1, s19
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX9-NEXT: s_sub_i32 s23, s16, 64
; GFX9-NEXT: s_sub_i32 s17, 64, s16
; GFX9-NEXT: s_cmp_lt_u32 s16, 64
-; GFX9-NEXT: s_cselect_b32 s29, 1, 0
+; GFX9-NEXT: s_cselect_b32 s28, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s16, 0
-; GFX9-NEXT: s_cselect_b32 s30, 1, 0
+; GFX9-NEXT: s_cselect_b32 s29, 1, 0
; GFX9-NEXT: s_lshl_b64 s[2:3], s[24:25], s16
; GFX9-NEXT: s_lshr_b64 s[26:27], s[24:25], s17
; GFX9-NEXT: s_lshl_b64 s[16:17], s[0:1], s16
; GFX9-NEXT: s_or_b64 s[16:17], s[26:27], s[16:17]
; GFX9-NEXT: s_lshl_b64 s[24:25], s[24:25], s23
-; GFX9-NEXT: s_cmp_lg_u32 s29, 0
+; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX9-NEXT: s_cselect_b64 s[16:17], s[16:17], s[24:25]
-; GFX9-NEXT: s_cmp_lg_u32 s30, 0
+; GFX9-NEXT: s_cmp_lg_u32 s29, 0
; GFX9-NEXT: s_cselect_b64 s[16:17], s[0:1], s[16:17]
; GFX9-NEXT: s_sub_i32 s26, s22, 64
; GFX9-NEXT: s_sub_i32 s24, 64, s22
; GFX9-NEXT: s_cmp_lt_u32 s22, 64
; GFX9-NEXT: s_cselect_b32 s27, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s22, 0
-; GFX9-NEXT: s_cselect_b32 s29, 1, 0
+; GFX9-NEXT: s_cselect_b32 s28, 1, 0
; GFX9-NEXT: s_lshr_b64 s[0:1], s[10:11], s22
; GFX9-NEXT: s_lshl_b64 s[24:25], s[10:11], s24
; GFX9-NEXT: s_lshr_b64 s[22:23], s[8:9], s22
@@ -6245,7 +6134,7 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], s26
; GFX9-NEXT: s_cmp_lg_u32 s27, 0
; GFX9-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11]
-; GFX9-NEXT: s_cmp_lg_u32 s29, 0
+; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
; GFX9-NEXT: s_cmp_lg_u32 s27, 0
; GFX9-NEXT: s_cselect_b64 s[10:11], s[0:1], 0
@@ -6254,9 +6143,9 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX9-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX9-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX9-NEXT: s_lshl_b64 s[16:17], s[4:5], 1
-; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s28
-; GFX9-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
-; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
+; GFX9-NEXT: s_lshr_b32 s18, s5, 31
+; GFX9-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
+; GFX9-NEXT: s_or_b64 s[4:5], s[18:19], s[4:5]
; GFX9-NEXT: s_sub_i32 s9, s10, 64
; GFX9-NEXT: s_sub_i32 s11, 64, s10
; GFX9-NEXT: s_cmp_lt_u32 s10, 64
@@ -6296,36 +6185,37 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
;
; GFX10-LABEL: s_fshr_v2i128:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_mov_b64 s[18:19], 0x7f
-; GFX10-NEXT: s_sub_i32 s28, 64, 1
+; GFX10-NEXT: s_mov_b32 s19, 0
+; GFX10-NEXT: s_movk_i32 s18, 0x7f
+; GFX10-NEXT: s_lshr_b32 s24, s1, 31
; GFX10-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX10-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
-; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s28
+; GFX10-NEXT: s_mov_b32 s25, s19
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX10-NEXT: s_or_b64 s[2:3], s[24:25], s[2:3]
; GFX10-NEXT: s_sub_i32 s23, s16, 64
; GFX10-NEXT: s_sub_i32 s17, 64, s16
; GFX10-NEXT: s_cmp_lt_u32 s16, 64
-; GFX10-NEXT: s_cselect_b32 s29, 1, 0
+; GFX10-NEXT: s_cselect_b32 s28, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s16, 0
-; GFX10-NEXT: s_cselect_b32 s30, 1, 0
+; GFX10-NEXT: s_cselect_b32 s29, 1, 0
; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s17
; GFX10-NEXT: s_lshl_b64 s[26:27], s[2:3], s16
; GFX10-NEXT: s_lshl_b64 s[16:17], s[0:1], s16
; GFX10-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s23
-; GFX10-NEXT: s_cmp_lg_u32 s29, 0
+; GFX10-NEXT: s_cmp_lg_u32 s28, 0
; GFX10-NEXT: s_cselect_b64 s[16:17], s[16:17], 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1]
-; GFX10-NEXT: s_cmp_lg_u32 s30, 0
+; GFX10-NEXT: s_cmp_lg_u32 s29, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX10-NEXT: s_sub_i32 s26, s22, 64
; GFX10-NEXT: s_sub_i32 s23, 64, s22
; GFX10-NEXT: s_cmp_lt_u32 s22, 64
; GFX10-NEXT: s_cselect_b32 s27, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s22, 0
-; GFX10-NEXT: s_cselect_b32 s29, 1, 0
+; GFX10-NEXT: s_cselect_b32 s28, 1, 0
; GFX10-NEXT: s_lshr_b64 s[0:1], s[8:9], s22
; GFX10-NEXT: s_lshl_b64 s[24:25], s[10:11], s23
; GFX10-NEXT: s_lshr_b64 s[22:23], s[10:11], s22
@@ -6333,18 +6223,18 @@ define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inr
; GFX10-NEXT: s_lshr_b64 s[10:11], s[10:11], s26
; GFX10-NEXT: s_cmp_lg_u32 s27, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11]
-; GFX10-NEXT: s_cmp_lg_u32 s29, 0
+; GFX10-NEXT: s_cmp_lg_u32 s28, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s27, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[22:23], 0
; GFX10-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
-; GFX10-NEXT: s_or_b64 s[0:1], s[16:17], s[0:1]
-; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s28
-; GFX10-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX10-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
+; GFX10-NEXT: s_lshr_b32 s18, s5, 31
+; GFX10-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
+; GFX10-NEXT: s_or_b64 s[0:1], s[16:17], s[0:1]
; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], 1
-; GFX10-NEXT: s_or_b64 s[6:7], s[16:17], s[6:7]
+; GFX10-NEXT: s_or_b64 s[6:7], s[18:19], s[6:7]
; GFX10-NEXT: s_sub_i32 s9, s10, 64
; GFX10-NEXT: s_sub_i32 s11, 64, s10
; GFX10-NEXT: s_cmp_lt_u32 s10, 64
@@ -6389,17 +6279,15 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX6-LABEL: v_fshr_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: s_sub_i32 s6, 64, 1
-; GFX6-NEXT: v_lshr_b64 v[17:18], v[0:1], s6
-; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
-; GFX6-NEXT: s_movk_i32 s7, 0x7f
-; GFX6-NEXT: v_or_b32_e32 v2, v17, v2
+; GFX6-NEXT: s_movk_i32 s6, 0x7f
; GFX6-NEXT: v_xor_b32_e32 v17, -1, v16
-; GFX6-NEXT: v_and_b32_e32 v23, s7, v17
+; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
+; GFX6-NEXT: v_and_b32_e32 v23, s6, v17
+; GFX6-NEXT: v_lshrrev_b32_e32 v17, 31, v1
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
-; GFX6-NEXT: v_or_b32_e32 v3, v18, v3
+; GFX6-NEXT: v_or_b32_e32 v2, v17, v2
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, 64, v23
-; GFX6-NEXT: v_and_b32_e32 v24, s7, v16
+; GFX6-NEXT: v_and_b32_e32 v24, s6, v16
; GFX6-NEXT: v_lshr_b64 v[17:18], v[0:1], v17
; GFX6-NEXT: v_lshl_b64 v[21:22], v[2:3], v23
; GFX6-NEXT: v_sub_i32_e32 v16, vcc, 64, v24
@@ -6434,67 +6322,64 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX6-NEXT: v_or_b32_e32 v0, v25, v2
; GFX6-NEXT: v_or_b32_e32 v2, v17, v8
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v20
+; GFX6-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GFX6-NEXT: v_or_b32_e32 v1, v18, v3
; GFX6-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX6-NEXT: v_and_b32_e32 v17, s7, v8
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], s6
-; GFX6-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
-; GFX6-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
-; GFX6-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX6-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v17
-; GFX6-NEXT: v_lshr_b64 v[8:9], v[4:5], v8
+; GFX6-NEXT: v_and_b32_e32 v17, s6, v8
+; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v5
+; GFX6-NEXT: v_or_b32_e32 v6, v4, v6
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 64, v17
+; GFX6-NEXT: v_lshr_b64 v[4:5], v[8:9], v4
; GFX6-NEXT: v_lshl_b64 v[10:11], v[6:7], v17
; GFX6-NEXT: v_subrev_i32_e32 v18, vcc, 64, v17
-; GFX6-NEXT: v_or_b32_e32 v10, v8, v10
-; GFX6-NEXT: v_or_b32_e32 v11, v9, v11
-; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v17
-; GFX6-NEXT: v_lshl_b64 v[4:5], v[4:5], v18
+; GFX6-NEXT: v_or_b32_e32 v10, v4, v10
+; GFX6-NEXT: v_or_b32_e32 v11, v5, v11
+; GFX6-NEXT: v_lshl_b64 v[4:5], v[8:9], v17
+; GFX6-NEXT: v_lshl_b64 v[8:9], v[8:9], v18
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17
-; GFX6-NEXT: v_and_b32_e32 v16, s7, v20
-; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX6-NEXT: v_and_b32_e32 v16, s6, v20
+; GFX6-NEXT: v_cndmask_b32_e32 v18, 0, v4, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v19, 0, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v10, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v11, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v17
-; GFX6-NEXT: v_cndmask_b32_e32 v10, v4, v6, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v11, v5, v7, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v9, v5, v7, vcc
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 64, v16
; GFX6-NEXT: v_lshr_b64 v[4:5], v[12:13], v16
; GFX6-NEXT: v_lshl_b64 v[6:7], v[14:15], v6
-; GFX6-NEXT: v_subrev_i32_e32 v17, vcc, 64, v16
-; GFX6-NEXT: v_or_b32_e32 v18, v4, v6
-; GFX6-NEXT: v_or_b32_e32 v19, v5, v7
-; GFX6-NEXT: v_lshr_b64 v[6:7], v[14:15], v17
+; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, 64, v16
+; GFX6-NEXT: v_or_b32_e32 v11, v4, v6
+; GFX6-NEXT: v_or_b32_e32 v17, v5, v7
+; GFX6-NEXT: v_lshr_b64 v[6:7], v[14:15], v10
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
; GFX6-NEXT: v_lshr_b64 v[4:5], v[14:15], v16
-; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v18, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc
; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v19, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[4:5]
+; GFX6-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[4:5]
-; GFX6-NEXT: v_cndmask_b32_e32 v12, 0, v4, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v13, 0, v5, vcc
-; GFX6-NEXT: v_or_b32_e32 v4, v8, v6
-; GFX6-NEXT: v_or_b32_e32 v5, v9, v7
-; GFX6-NEXT: v_or_b32_e32 v6, v10, v12
-; GFX6-NEXT: v_or_b32_e32 v7, v11, v13
+; GFX6-NEXT: v_cndmask_b32_e32 v11, 0, v5, vcc
+; GFX6-NEXT: v_or_b32_e32 v4, v18, v6
+; GFX6-NEXT: v_or_b32_e32 v5, v19, v7
+; GFX6-NEXT: v_or_b32_e32 v6, v8, v10
+; GFX6-NEXT: v_or_b32_e32 v7, v9, v11
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_fshr_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: s_sub_i32 s6, 64, 1
-; GFX8-NEXT: v_lshrrev_b64 v[17:18], s6, v[0:1]
-; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX8-NEXT: s_movk_i32 s7, 0x7f
-; GFX8-NEXT: v_or_b32_e32 v2, v17, v2
+; GFX8-NEXT: s_movk_i32 s6, 0x7f
; GFX8-NEXT: v_xor_b32_e32 v17, -1, v16
-; GFX8-NEXT: v_and_b32_e32 v23, s7, v17
+; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX8-NEXT: v_and_b32_e32 v23, s6, v17
+; GFX8-NEXT: v_lshrrev_b32_e32 v17, 31, v1
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX8-NEXT: v_or_b32_e32 v3, v18, v3
+; GFX8-NEXT: v_or_b32_e32 v2, v17, v2
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, 64, v23
-; GFX8-NEXT: v_and_b32_e32 v24, s7, v16
+; GFX8-NEXT: v_and_b32_e32 v24, s6, v16
; GFX8-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v24
@@ -6529,67 +6414,64 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX8-NEXT: v_or_b32_e32 v0, v25, v2
; GFX8-NEXT: v_or_b32_e32 v2, v17, v8
; GFX8-NEXT: v_xor_b32_e32 v8, -1, v20
+; GFX8-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
; GFX8-NEXT: v_or_b32_e32 v1, v18, v3
; GFX8-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX8-NEXT: v_and_b32_e32 v17, s7, v8
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], s6, v[4:5]
-; GFX8-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
-; GFX8-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
-; GFX8-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX8-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v17
-; GFX8-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5]
+; GFX8-NEXT: v_and_b32_e32 v17, s6, v8
+; GFX8-NEXT: v_lshlrev_b64 v[8:9], 1, v[4:5]
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v5
+; GFX8-NEXT: v_or_b32_e32 v6, v4, v6
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 64, v17
+; GFX8-NEXT: v_lshrrev_b64 v[4:5], v4, v[8:9]
; GFX8-NEXT: v_lshlrev_b64 v[10:11], v17, v[6:7]
; GFX8-NEXT: v_subrev_u32_e32 v18, vcc, 64, v17
-; GFX8-NEXT: v_or_b32_e32 v10, v8, v10
-; GFX8-NEXT: v_or_b32_e32 v11, v9, v11
-; GFX8-NEXT: v_lshlrev_b64 v[8:9], v17, v[4:5]
-; GFX8-NEXT: v_lshlrev_b64 v[4:5], v18, v[4:5]
+; GFX8-NEXT: v_or_b32_e32 v10, v4, v10
+; GFX8-NEXT: v_or_b32_e32 v11, v5, v11
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v17, v[8:9]
+; GFX8-NEXT: v_lshlrev_b64 v[8:9], v18, v[8:9]
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17
-; GFX8-NEXT: v_and_b32_e32 v16, s7, v20
-; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX8-NEXT: v_and_b32_e32 v16, s6, v20
+; GFX8-NEXT: v_cndmask_b32_e32 v18, 0, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v19, 0, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v10, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v11, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v17
-; GFX8-NEXT: v_cndmask_b32_e32 v10, v4, v6, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v11, v5, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v5, v7, vcc
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 64, v16
; GFX8-NEXT: v_lshrrev_b64 v[4:5], v16, v[12:13]
; GFX8-NEXT: v_lshlrev_b64 v[6:7], v6, v[14:15]
-; GFX8-NEXT: v_subrev_u32_e32 v17, vcc, 64, v16
-; GFX8-NEXT: v_or_b32_e32 v18, v4, v6
-; GFX8-NEXT: v_or_b32_e32 v19, v5, v7
-; GFX8-NEXT: v_lshrrev_b64 v[6:7], v17, v[14:15]
+; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, 64, v16
+; GFX8-NEXT: v_or_b32_e32 v11, v4, v6
+; GFX8-NEXT: v_or_b32_e32 v17, v5, v7
+; GFX8-NEXT: v_lshrrev_b64 v[6:7], v10, v[14:15]
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
; GFX8-NEXT: v_lshrrev_b64 v[4:5], v16, v[14:15]
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v18, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v19, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v12, 0, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v13, 0, v5, vcc
-; GFX8-NEXT: v_or_b32_e32 v4, v8, v6
-; GFX8-NEXT: v_or_b32_e32 v5, v9, v7
-; GFX8-NEXT: v_or_b32_e32 v6, v10, v12
-; GFX8-NEXT: v_or_b32_e32 v7, v11, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v11, 0, v5, vcc
+; GFX8-NEXT: v_or_b32_e32 v4, v18, v6
+; GFX8-NEXT: v_or_b32_e32 v5, v19, v7
+; GFX8-NEXT: v_or_b32_e32 v6, v8, v10
+; GFX8-NEXT: v_or_b32_e32 v7, v9, v11
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_sub_i32 s6, 64, 1
-; GFX9-NEXT: v_lshrrev_b64 v[17:18], s6, v[0:1]
-; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX9-NEXT: s_movk_i32 s7, 0x7f
-; GFX9-NEXT: v_or_b32_e32 v2, v17, v2
+; GFX9-NEXT: s_movk_i32 s6, 0x7f
; GFX9-NEXT: v_xor_b32_e32 v17, -1, v16
-; GFX9-NEXT: v_and_b32_e32 v23, s7, v17
+; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX9-NEXT: v_and_b32_e32 v23, s6, v17
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 31, v1
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX9-NEXT: v_or_b32_e32 v3, v18, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v17, v2
; GFX9-NEXT: v_sub_u32_e32 v17, 64, v23
-; GFX9-NEXT: v_and_b32_e32 v24, s7, v16
+; GFX9-NEXT: v_and_b32_e32 v24, s6, v16
; GFX9-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[21:22], v23, v[2:3]
; GFX9-NEXT: v_sub_u32_e32 v16, 64, v24
@@ -6624,119 +6506,114 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX9-NEXT: v_or_b32_e32 v0, v25, v2
; GFX9-NEXT: v_or_b32_e32 v2, v17, v8
; GFX9-NEXT: v_xor_b32_e32 v8, -1, v20
+; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
; GFX9-NEXT: v_or_b32_e32 v1, v18, v3
-; GFX9-NEXT: v_and_b32_e32 v17, s7, v8
+; GFX9-NEXT: v_and_b32_e32 v17, s6, v8
; GFX9-NEXT: v_or_b32_e32 v3, v16, v9
-; GFX9-NEXT: v_lshrrev_b64 v[8:9], s6, v[4:5]
-; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
-; GFX9-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
-; GFX9-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX9-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX9-NEXT: v_sub_u32_e32 v8, 64, v17
-; GFX9-NEXT: v_lshrrev_b64 v[8:9], v8, v[4:5]
+; GFX9-NEXT: v_lshlrev_b64 v[8:9], 1, v[4:5]
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v5
+; GFX9-NEXT: v_or_b32_e32 v6, v4, v6
+; GFX9-NEXT: v_sub_u32_e32 v4, 64, v17
+; GFX9-NEXT: v_lshrrev_b64 v[4:5], v4, v[8:9]
; GFX9-NEXT: v_lshlrev_b64 v[10:11], v17, v[6:7]
; GFX9-NEXT: v_subrev_u32_e32 v18, 64, v17
-; GFX9-NEXT: v_or_b32_e32 v10, v8, v10
-; GFX9-NEXT: v_or_b32_e32 v11, v9, v11
-; GFX9-NEXT: v_lshlrev_b64 v[8:9], v17, v[4:5]
-; GFX9-NEXT: v_lshlrev_b64 v[4:5], v18, v[4:5]
+; GFX9-NEXT: v_or_b32_e32 v10, v4, v10
+; GFX9-NEXT: v_or_b32_e32 v11, v5, v11
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], v17, v[8:9]
+; GFX9-NEXT: v_lshlrev_b64 v[8:9], v18, v[8:9]
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v17
-; GFX9-NEXT: v_and_b32_e32 v16, s7, v20
-; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
+; GFX9-NEXT: v_and_b32_e32 v16, s6, v20
+; GFX9-NEXT: v_cndmask_b32_e32 v18, 0, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v19, 0, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v10, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v11, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v17
-; GFX9-NEXT: v_cndmask_b32_e32 v10, v4, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v8, v4, v6, vcc
; GFX9-NEXT: v_sub_u32_e32 v6, 64, v16
-; GFX9-NEXT: v_cndmask_b32_e32 v11, v5, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v5, v7, vcc
; GFX9-NEXT: v_lshrrev_b64 v[4:5], v16, v[12:13]
; GFX9-NEXT: v_lshlrev_b64 v[6:7], v6, v[14:15]
-; GFX9-NEXT: v_subrev_u32_e32 v17, 64, v16
-; GFX9-NEXT: v_or_b32_e32 v18, v4, v6
-; GFX9-NEXT: v_or_b32_e32 v19, v5, v7
-; GFX9-NEXT: v_lshrrev_b64 v[6:7], v17, v[14:15]
+; GFX9-NEXT: v_subrev_u32_e32 v10, 64, v16
+; GFX9-NEXT: v_or_b32_e32 v11, v4, v6
+; GFX9-NEXT: v_or_b32_e32 v17, v5, v7
+; GFX9-NEXT: v_lshrrev_b64 v[6:7], v10, v[14:15]
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16
; GFX9-NEXT: v_lshrrev_b64 v[4:5], v16, v[14:15]
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v18, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v19, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v13, s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v12, 0, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v13, 0, v5, vcc
-; GFX9-NEXT: v_or_b32_e32 v4, v8, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v9, v7
-; GFX9-NEXT: v_or_b32_e32 v6, v10, v12
-; GFX9-NEXT: v_or_b32_e32 v7, v11, v13
+; GFX9-NEXT: v_cndmask_b32_e32 v11, 0, v5, vcc
+; GFX9-NEXT: v_or_b32_e32 v4, v18, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v19, v7
+; GFX9-NEXT: v_or_b32_e32 v6, v8, v10
+; GFX9-NEXT: v_or_b32_e32 v7, v9, v11
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fshr_v2i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v19, -1, v16
-; GFX10-NEXT: s_sub_i32 s5, 64, 1
-; GFX10-NEXT: s_movk_i32 s6, 0x7f
-; GFX10-NEXT: v_lshrrev_b64 v[17:18], s5, v[0:1]
+; GFX10-NEXT: v_xor_b32_e32 v17, -1, v16
+; GFX10-NEXT: s_movk_i32 s5, 0x7f
; GFX10-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX10-NEXT: v_and_b32_e32 v25, s6, v19
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
-; GFX10-NEXT: v_and_b32_e32 v26, s6, v16
+; GFX10-NEXT: v_and_b32_e32 v26, s5, v16
; GFX10-NEXT: v_lshlrev_b64 v[6:7], 1, v[6:7]
+; GFX10-NEXT: v_and_b32_e32 v25, s5, v17
+; GFX10-NEXT: v_lshrrev_b32_e32 v17, 31, v1
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX10-NEXT: v_subrev_nc_u32_e32 v27, 64, v26
+; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v26
+; GFX10-NEXT: v_sub_nc_u32_e32 v18, 64, v25
; GFX10-NEXT: v_or_b32_e32 v2, v17, v2
-; GFX10-NEXT: v_or_b32_e32 v3, v18, v3
-; GFX10-NEXT: v_sub_nc_u32_e32 v17, 64, v25
-; GFX10-NEXT: v_subrev_nc_u32_e32 v16, 64, v25
-; GFX10-NEXT: v_sub_nc_u32_e32 v19, 64, v26
+; GFX10-NEXT: v_subrev_nc_u32_e32 v19, 64, v25
; GFX10-NEXT: v_lshlrev_b64 v[23:24], v25, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[21:22], v25, v[2:3]
-; GFX10-NEXT: v_lshrrev_b64 v[17:18], v17, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v16, v[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
-; GFX10-NEXT: v_subrev_nc_u32_e32 v27, 64, v26
-; GFX10-NEXT: v_cmp_gt_u32_e64 s4, 64, v26
-; GFX10-NEXT: v_or_b32_e32 v21, v17, v21
+; GFX10-NEXT: v_lshrrev_b64 v[17:18], v18, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[21:22], v25, v[2:3]
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], v19, v[0:1]
+; GFX10-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc_lo
; GFX10-NEXT: v_or_b32_e32 v22, v18, v22
+; GFX10-NEXT: v_sub_nc_u32_e32 v18, 64, v26
+; GFX10-NEXT: v_or_b32_e32 v21, v17, v21
; GFX10-NEXT: v_lshrrev_b64 v[16:17], v26, v[8:9]
-; GFX10-NEXT: v_lshlrev_b64 v[18:19], v19, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo
+; GFX10-NEXT: v_lshlrev_b64 v[18:19], v18, v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v21, v0, v21, vcc_lo
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v27, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v25
; GFX10-NEXT: v_or_b32_e32 v16, v16, v18
; GFX10-NEXT: v_or_b32_e32 v17, v17, v19
; GFX10-NEXT: v_cndmask_b32_e32 v18, v21, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v3, vcc_lo
-; GFX10-NEXT: v_lshrrev_b64 v[2:3], v26, v[10:11]
-; GFX10-NEXT: v_cndmask_b32_e64 v10, v0, v16, s4
-; GFX10-NEXT: v_xor_b32_e32 v16, -1, v20
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v26
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v1, v17, s4
-; GFX10-NEXT: v_lshrrev_b64 v[0:1], s5, v[4:5]
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v16, s4
+; GFX10-NEXT: v_xor_b32_e32 v16, -1, v20
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v17, s4
+; GFX10-NEXT: v_lshrrev_b64 v[2:3], v26, v[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v8, 31, v5
+; GFX10-NEXT: v_and_b32_e32 v25, s5, v16
; GFX10-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
-; GFX10-NEXT: v_and_b32_e32 v25, s6, v16
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v16, v11, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s4
-; GFX10-NEXT: v_or_b32_e32 v6, v0, v6
-; GFX10-NEXT: v_or_b32_e32 v7, v1, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
+; GFX10-NEXT: v_or_b32_e32 v0, v23, v0
+; GFX10-NEXT: v_or_b32_e32 v6, v8, v6
; GFX10-NEXT: v_sub_nc_u32_e32 v9, 64, v25
-; GFX10-NEXT: v_or_b32_e32 v0, v23, v8
-; GFX10-NEXT: v_and_b32_e32 v23, s6, v20
+; GFX10-NEXT: v_and_b32_e32 v23, s5, v20
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s4
; GFX10-NEXT: v_cndmask_b32_e64 v26, 0, v3, s4
; GFX10-NEXT: v_lshlrev_b64 v[10:11], v25, v[6:7]
; GFX10-NEXT: v_lshrrev_b64 v[8:9], v9, v[4:5]
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 64, v25
; GFX10-NEXT: v_sub_nc_u32_e32 v20, 64, v23
-; GFX10-NEXT: v_or_b32_e32 v1, v24, v16
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 64, v25
; GFX10-NEXT: v_or_b32_e32 v2, v18, v2
; GFX10-NEXT: v_lshlrev_b64 v[16:17], v25, v[4:5]
+; GFX10-NEXT: v_lshrrev_b64 v[18:19], v23, v[12:13]
; GFX10-NEXT: v_or_b32_e32 v10, v8, v10
; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 64, v23
-; GFX10-NEXT: v_lshrrev_b64 v[18:19], v23, v[12:13]
; GFX10-NEXT: v_lshlrev_b64 v[20:21], v20, v[14:15]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v25
; GFX10-NEXT: v_lshlrev_b64 v[3:4], v3, v[4:5]
@@ -6760,11 +6637,12 @@ define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, v4, s4
; GFX10-NEXT: v_cndmask_b32_e64 v8, v9, v13, s5
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, v3, s4
-; GFX10-NEXT: v_or_b32_e32 v3, v22, v26
+; GFX10-NEXT: v_or_b32_e32 v1, v24, v1
; GFX10-NEXT: v_or_b32_e32 v4, v11, v5
-; GFX10-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX10-NEXT: v_or_b32_e32 v3, v22, v26
; GFX10-NEXT: v_or_b32_e32 v5, v14, v8
; GFX10-NEXT: v_or_b32_e32 v6, v6, v9
+; GFX10-NEXT: v_or_b32_e32 v7, v7, v10
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index 9ccc2ee540f26..ebdac64a8301b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -4797,13 +4797,11 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
; GFX6-NEXT: s_ashr_i32 s3, s9, 31
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
-; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64
-; GFX6-NEXT: s_ashr_i64 s[0:1], s[8:9], s0
-; GFX6-NEXT: s_add_u32 s0, s0, 0
-; GFX6-NEXT: s_cselect_b32 s2, 1, 0
-; GFX6-NEXT: s_and_b32 s2, s2, 1
-; GFX6-NEXT: s_cmp_lg_u32 s2, 0
-; GFX6-NEXT: s_addc_u32 s1, s1, 0
+; GFX6-NEXT: s_add_u32 s0, s3, 0
+; GFX6-NEXT: s_cselect_b32 s1, 1, 0
+; GFX6-NEXT: s_and_b32 s1, s1, 1
+; GFX6-NEXT: s_cmp_lg_u32 s1, 0
+; GFX6-NEXT: s_addc_u32 s1, s3, 0
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_and_b32 s2, s2, 1
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
@@ -4867,15 +4865,13 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
-; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64
; GFX8-NEXT: s_ashr_i32 s3, s9, 31
-; GFX8-NEXT: s_ashr_i64 s[0:1], s[8:9], s0
-; GFX8-NEXT: s_add_u32 s0, s0, 0
-; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: s_and_b32 s2, s2, 1
-; GFX8-NEXT: s_cmp_lg_u32 s2, 0
-; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
+; GFX8-NEXT: s_add_u32 s0, s3, 0
+; GFX8-NEXT: s_cselect_b32 s1, 1, 0
+; GFX8-NEXT: s_and_b32 s1, s1, 1
+; GFX8-NEXT: s_cmp_lg_u32 s1, 0
+; GFX8-NEXT: s_addc_u32 s1, s3, 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_and_b32 s2, s2, 1
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
@@ -4939,15 +4935,13 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
-; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64
; GFX9-NEXT: s_ashr_i32 s3, s9, 31
-; GFX9-NEXT: s_ashr_i64 s[0:1], s[8:9], s0
-; GFX9-NEXT: s_add_u32 s0, s0, 0
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_and_b32 s2, s2, 1
-; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
+; GFX9-NEXT: s_add_u32 s0, s3, 0
+; GFX9-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-NEXT: s_and_b32 s1, s1, 1
+; GFX9-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-NEXT: s_addc_u32 s1, s3, 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_and_b32 s2, s2, 1
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
@@ -5011,25 +5005,23 @@ define amdgpu_ps i128 @s_saddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: s_and_b32 s0, 1, s1
-; GFX10-NEXT: s_sub_i32 s1, 0x7f, 64
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0
-; GFX10-NEXT: s_ashr_i64 s[0:1], s[8:9], s1
-; GFX10-NEXT: s_add_u32 s0, s0, 0
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_add_u32 s0, s3, 0
+; GFX10-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-NEXT: s_and_b32 s1, s1, 1
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT: s_and_b32 s2, s2, 1
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: v_mov_b32_e32 v1, s4
-; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: s_addc_u32 s1, s1, 0
+; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: s_and_b32 s2, s2, 1
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
; GFX10-NEXT: s_addc_u32 s2, s3, 0
-; GFX10-NEXT: s_cselect_b32 s6, 1, 0
+; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: s_and_b32 s4, s6, 1
+; GFX10-NEXT: s_and_b32 s4, s4, 1
; GFX10-NEXT: s_cmp_lg_u32 s4, 0
; GFX10-NEXT: s_addc_u32 s3, s3, 0x80000000
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo
@@ -5056,30 +5048,28 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v2, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v3, vcc
; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1]
-; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64
+; GFX6-NEXT: v_bfrev_b32_e32 v8, 1
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[4:5]
-; GFX6-NEXT: v_bfrev_b32_e32 v8, 1
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3]
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, 0, vcc
-; GFX6-NEXT: v_xor_b32_e32 v6, v2, v6
-; GFX6-NEXT: v_ashr_i64 v[2:3], v[4:5], s0
-; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v5
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0, v2
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v7, vcc
-; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
-; GFX6-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_xor_b32_e32 v2, v2, v6
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0, v3
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
+; GFX6-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v9, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: saddsat_i128_sv:
@@ -5092,30 +5082,28 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v4, v2, vcc
; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v5, v3, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1]
-; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64
+; GFX8-NEXT: v_bfrev_b32_e32 v8, 1
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[4:5]
-; GFX8-NEXT: v_bfrev_b32_e32 v8, 1
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3]
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX8-NEXT: v_cndmask_b32_e64 v2, v7, 0, vcc
-; GFX8-NEXT: v_xor_b32_e32 v6, v2, v6
-; GFX8-NEXT: v_ashrrev_i64 v[2:3], s0, v[4:5]
-; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v5
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0, v2
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v7, vcc
-; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
-; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_xor_b32_e32 v2, v2, v6
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0, v3
+; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
+; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
+; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: saddsat_i128_sv:
@@ -5128,30 +5116,28 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v3, vcc
; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1]
-; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64
+; GFX9-NEXT: v_bfrev_b32_e32 v8, 1
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[4:5]
-; GFX9-NEXT: v_bfrev_b32_e32 v8, 1
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
+; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX9-NEXT: v_cndmask_b32_e64 v2, v7, 0, vcc
-; GFX9-NEXT: v_xor_b32_e32 v6, v2, v6
-; GFX9-NEXT: v_ashrrev_i64 v[2:3], s0, v[4:5]
-; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v5
-; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v7, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v8, vcc
-; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v2, v2, v6
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 0, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v3, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v3, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: saddsat_i128_sv:
@@ -5161,7 +5147,6 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
-; GFX10-NEXT: s_sub_i32 s0, 0x7f, 64
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
@@ -5170,20 +5155,19 @@ define amdgpu_ps <4 x float> @saddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT: v_ashrrev_i32_e32 v7, 31, v5
+; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc_lo
-; GFX10-NEXT: v_xor_b32_e32 v6, v2, v6
-; GFX10-NEXT: v_ashrrev_i64 v[2:3], s0, v[4:5]
-; GFX10-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v6
-; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0x80000000, v7, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v3, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v6, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v7, s0
+; GFX10-NEXT: v_xor_b32_e32 v2, v2, v6
+; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v3, 0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v3, vcc_lo
+; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v2
+; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0x80000000, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v6, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v7, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v2, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v3, s0
; GFX10-NEXT: ; return to shader part epilog
%result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
@@ -5207,24 +5191,22 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX6-NEXT: v_bfrev_b32_e32 v8, 1
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
-; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v7
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
-; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64
-; GFX6-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX6-NEXT: v_ashr_i64 v[0:1], v[6:7], s0
-; GFX6-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0, v1
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: saddsat_i128_vs:
@@ -5249,21 +5231,19 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX8-NEXT: s_and_b32 s0, 1, s4
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
-; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64
-; GFX8-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX8-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7]
-; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v7
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0, v1
+; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX8-NEXT: v_bfrev_b32_e32 v8, 1
-; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
+; GFX8-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: saddsat_i128_vs:
@@ -5288,21 +5268,19 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX9-NEXT: s_and_b32 s0, 1, s4
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
-; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64
-; GFX9-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX9-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7]
-; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v7
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0
-; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: v_bfrev_b32_e32 v8, 1
-; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v3, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v1, v8, vcc
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: saddsat_i128_vs:
@@ -5322,22 +5300,20 @@ define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v8, 0, s0
-; GFX10-NEXT: s_sub_i32 s0, 0x7f, 64
-; GFX10-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX10-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7]
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v2
-; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0x80000000, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v1, 0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v2, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v3, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX10-NEXT: ; return to shader part epilog
%result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
@@ -5353,30 +5329,28 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX6-NEXT: v_addc_u32_e32 v16, vcc, v2, v10, vcc
; GFX6-NEXT: v_addc_u32_e32 v17, vcc, v3, v11, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1]
-; GFX6-NEXT: s_sub_i32 s4, 0x7f, 64
+; GFX6-NEXT: v_bfrev_b32_e32 v18, 1
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[16:17], v[2:3]
-; GFX6-NEXT: v_bfrev_b32_e32 v18, 1
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[16:17], v[2:3]
-; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v17
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX6-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX6-NEXT: v_ashr_i64 v[0:1], v[16:17], s4
-; GFX6-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v18, vcc
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v17
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0, v1
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GFX6-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
+; GFX6-NEXT: v_addc_u32_e32 v11, vcc, v1, v18, vcc
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v16, v10, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v17, v11, vcc
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v4, v12
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v5, v13, vcc
; GFX6-NEXT: v_addc_u32_e32 v10, vcc, v6, v14, vcc
@@ -5386,24 +5360,23 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
-; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v11
; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX6-NEXT: v_xor_b32_e32 v6, v5, v4
-; GFX6-NEXT: v_ashr_i64 v[4:5], v[10:11], s4
-; GFX6-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0, v4
-; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GFX6-NEXT: v_addc_u32_e32 v12, vcc, 0, v7, vcc
-; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v18, vcc
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
+; GFX6-NEXT: v_xor_b32_e32 v4, v5, v4
+; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v11
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0, v5
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
+; GFX6-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc
+; GFX6-NEXT: v_addc_u32_e32 v13, vcc, v5, v18, vcc
+; GFX6-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_saddsat_v2i128:
@@ -5414,30 +5387,28 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX8-NEXT: v_addc_u32_e32 v16, vcc, v2, v10, vcc
; GFX8-NEXT: v_addc_u32_e32 v17, vcc, v3, v11, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1]
-; GFX8-NEXT: s_sub_i32 s4, 0x7f, 64
+; GFX8-NEXT: v_bfrev_b32_e32 v18, 1
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[16:17], v[2:3]
-; GFX8-NEXT: v_bfrev_b32_e32 v18, 1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[16:17], v[2:3]
-; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v17
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX8-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX8-NEXT: v_ashrrev_i64 v[0:1], s4, v[16:17]
-; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v18, vcc
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v17
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0, v1
+; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GFX8-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
+; GFX8-NEXT: v_addc_u32_e32 v11, vcc, v1, v18, vcc
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v16, v10, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v11, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v4, v12
; GFX8-NEXT: v_addc_u32_e32 v9, vcc, v5, v13, vcc
; GFX8-NEXT: v_addc_u32_e32 v10, vcc, v6, v14, vcc
@@ -5447,24 +5418,23 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
-; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v11
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX8-NEXT: v_xor_b32_e32 v6, v5, v4
-; GFX8-NEXT: v_ashrrev_i64 v[4:5], s4, v[10:11]
-; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0, v4
-; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GFX8-NEXT: v_addc_u32_e32 v12, vcc, 0, v7, vcc
-; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v18, vcc
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
+; GFX8-NEXT: v_xor_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v11
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0, v5
+; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
+; GFX8-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc
+; GFX8-NEXT: v_addc_u32_e32 v13, vcc, v5, v18, vcc
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_saddsat_v2i128:
@@ -5475,30 +5445,28 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, v2, v10, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v17, vcc, v3, v11, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1]
-; GFX9-NEXT: s_sub_i32 s4, 0x7f, 64
+; GFX9-NEXT: v_bfrev_b32_e32 v18, 1
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[16:17], v[2:3]
-; GFX9-NEXT: v_bfrev_b32_e32 v18, 1
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[16:17], v[2:3]
-; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v17
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
-; GFX9-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX9-NEXT: v_ashrrev_i64 v[0:1], s4, v[16:17]
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0
-; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v3, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v18, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v17
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v1, v18, vcc
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v16, v10, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v11, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v4, v12
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v5, v13, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v6, v14, vcc
@@ -5508,24 +5476,23 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
-; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v11
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc
-; GFX9-NEXT: v_xor_b32_e32 v6, v5, v4
-; GFX9-NEXT: v_ashrrev_i64 v[4:5], s4, v[10:11]
-; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0, v4
-; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v7, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v18, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
+; GFX9-NEXT: v_xor_b32_e32 v4, v5, v4
+; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v11
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 0, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v5, v18, vcc
+; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_v2i128:
@@ -5533,7 +5500,6 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v0, v8
-; GFX10-NEXT: s_sub_i32 s6, 0x7f, 64
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v9, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v16, vcc_lo, v2, v10, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, v3, v11, vcc_lo
@@ -5544,49 +5510,47 @@ define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[2:3]
-; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v17
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v1, v18, 0, vcc_lo
; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, v4, v12
; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v5, v13, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, v6, v14, vcc_lo
-; GFX10-NEXT: v_xor_b32_e32 v2, v1, v0
+; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[10:11], v[4:5]
-; GFX10-NEXT: v_ashrrev_i64 v[0:1], s6, v[16:17]
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v17
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_cmp_eq_u64_e64 s5, v[12:13], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[12:13], v[6:7]
-; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v1, 0
+; GFX10-NEXT: v_ashrrev_i32_e32 v7, 31, v13
+; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, s4
-; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v4, s5
+; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v4, s5
; GFX10-NEXT: v_cmp_eq_u64_e64 s5, 0, v[14:15]
-; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0x80000000, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, v1, s4
+; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, v3, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, 0, s5
-; GFX10-NEXT: v_xor_b32_e32 v7, v4, v2
-; GFX10-NEXT: v_ashrrev_i64 v[3:4], s6, v[12:13]
+; GFX10-NEXT: v_xor_b32_e32 v4, v4, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v8, v2, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, v16, v5, s4
-; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v13
-; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
-; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v3, 0
+; GFX10-NEXT: v_and_b32_e32 v3, 1, v4
+; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v7, 0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v7, vcc_lo
+; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v3
+; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0x80000000, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v17, v6, s4
-; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v4, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v7
-; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v14, vcc_lo, 0x80000000, v5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, v8, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, v7, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, v9, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, v14, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v10, v4, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v11, v5, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, v8, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v13, v7, s5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
@@ -5620,25 +5584,23 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[16:17], v[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0
-; GFX6-NEXT: s_sub_i32 s10, 0x7f, 64
-; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
; GFX6-NEXT: s_ashr_i32 s3, s17, 31
-; GFX6-NEXT: s_ashr_i64 s[0:1], s[16:17], s10
-; GFX6-NEXT: s_add_u32 s0, s0, 0
-; GFX6-NEXT: s_cselect_b32 s2, 1, 0
-; GFX6-NEXT: s_and_b32 s2, s2, 1
-; GFX6-NEXT: s_cmp_lg_u32 s2, 0
-; GFX6-NEXT: s_addc_u32 s1, s1, 0
+; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
+; GFX6-NEXT: s_add_u32 s0, s3, 0
+; GFX6-NEXT: s_cselect_b32 s1, 1, 0
+; GFX6-NEXT: s_and_b32 s1, s1, 1
+; GFX6-NEXT: s_cmp_lg_u32 s1, 0
+; GFX6-NEXT: s_addc_u32 s1, s3, 0
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_and_b32 s2, s2, 1
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
; GFX6-NEXT: s_addc_u32 s2, s3, 0
-; GFX6-NEXT: s_cselect_b32 s18, 1, 0
-; GFX6-NEXT: s_and_b32 s18, s18, 1
-; GFX6-NEXT: s_brev_b32 s11, 1
-; GFX6-NEXT: s_cmp_lg_u32 s18, 0
+; GFX6-NEXT: s_cselect_b32 s11, 1, 0
+; GFX6-NEXT: s_and_b32 s11, s11, 1
+; GFX6-NEXT: s_brev_b32 s10, 1
+; GFX6-NEXT: s_cmp_lg_u32 s11, 0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
-; GFX6-NEXT: s_addc_u32 s3, s3, s11
+; GFX6-NEXT: s_addc_u32 s3, s3, s10
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_add_u32 s0, s4, s12
@@ -5681,12 +5643,11 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: v_cmp_eq_u64_e64 s[4:5], s[14:15], 0
; GFX6-NEXT: s_ashr_i32 s7, s3, 31
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
-; GFX6-NEXT: s_ashr_i64 s[4:5], s[2:3], s10
-; GFX6-NEXT: s_add_u32 s4, s4, 0
-; GFX6-NEXT: s_cselect_b32 s6, 1, 0
-; GFX6-NEXT: s_and_b32 s6, s6, 1
-; GFX6-NEXT: s_cmp_lg_u32 s6, 0
-; GFX6-NEXT: s_addc_u32 s5, s5, 0
+; GFX6-NEXT: s_add_u32 s4, s7, 0
+; GFX6-NEXT: s_cselect_b32 s5, 1, 0
+; GFX6-NEXT: s_and_b32 s5, s5, 1
+; GFX6-NEXT: s_cmp_lg_u32 s5, 0
+; GFX6-NEXT: s_addc_u32 s5, s7, 0
; GFX6-NEXT: s_cselect_b32 s6, 1, 0
; GFX6-NEXT: s_and_b32 s6, s6, 1
; GFX6-NEXT: s_cmp_lg_u32 s6, 0
@@ -5699,7 +5660,7 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: v_mov_b32_e32 v3, s0
; GFX6-NEXT: v_mov_b32_e32 v8, s1
-; GFX6-NEXT: s_addc_u32 s7, s7, s11
+; GFX6-NEXT: s_addc_u32 s7, s7, s10
; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_mov_b32_e32 v2, s5
@@ -5754,25 +5715,23 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
-; GFX8-NEXT: s_sub_i32 s10, 0x7f, 64
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
; GFX8-NEXT: s_ashr_i32 s3, s17, 31
-; GFX8-NEXT: s_ashr_i64 s[0:1], s[16:17], s10
-; GFX8-NEXT: s_add_u32 s0, s0, 0
-; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: s_and_b32 s2, s2, 1
-; GFX8-NEXT: s_cmp_lg_u32 s2, 0
-; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
+; GFX8-NEXT: s_add_u32 s0, s3, 0
+; GFX8-NEXT: s_cselect_b32 s1, 1, 0
+; GFX8-NEXT: s_and_b32 s1, s1, 1
+; GFX8-NEXT: s_cmp_lg_u32 s1, 0
+; GFX8-NEXT: s_addc_u32 s1, s3, 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_and_b32 s2, s2, 1
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
; GFX8-NEXT: s_addc_u32 s2, s3, 0
-; GFX8-NEXT: s_cselect_b32 s18, 1, 0
-; GFX8-NEXT: s_and_b32 s18, s18, 1
-; GFX8-NEXT: s_brev_b32 s11, 1
-; GFX8-NEXT: s_cmp_lg_u32 s18, 0
+; GFX8-NEXT: s_cselect_b32 s11, 1, 0
+; GFX8-NEXT: s_and_b32 s11, s11, 1
+; GFX8-NEXT: s_brev_b32 s10, 1
+; GFX8-NEXT: s_cmp_lg_u32 s11, 0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: s_addc_u32 s3, s3, s11
+; GFX8-NEXT: s_addc_u32 s3, s3, s10
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: s_add_u32 s0, s4, s12
@@ -5819,14 +5778,13 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX8-NEXT: s_and_b32 s4, 1, s6
; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX8-NEXT: s_ashr_i32 s7, s3, 31
-; GFX8-NEXT: s_ashr_i64 s[4:5], s[2:3], s10
-; GFX8-NEXT: s_add_u32 s4, s4, 0
-; GFX8-NEXT: s_cselect_b32 s6, 1, 0
-; GFX8-NEXT: s_and_b32 s6, s6, 1
-; GFX8-NEXT: s_cmp_lg_u32 s6, 0
-; GFX8-NEXT: s_addc_u32 s5, s5, 0
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
+; GFX8-NEXT: s_add_u32 s4, s7, 0
+; GFX8-NEXT: s_cselect_b32 s5, 1, 0
+; GFX8-NEXT: s_and_b32 s5, s5, 1
+; GFX8-NEXT: s_cmp_lg_u32 s5, 0
+; GFX8-NEXT: s_addc_u32 s5, s7, 0
; GFX8-NEXT: s_cselect_b32 s6, 1, 0
; GFX8-NEXT: s_and_b32 s6, s6, 1
; GFX8-NEXT: s_cmp_lg_u32 s6, 0
@@ -5839,7 +5797,7 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_mov_b32_e32 v3, s0
; GFX8-NEXT: v_mov_b32_e32 v8, s1
-; GFX8-NEXT: s_addc_u32 s7, s7, s11
+; GFX8-NEXT: s_addc_u32 s7, s7, s10
; GFX8-NEXT: v_mov_b32_e32 v1, s4
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_mov_b32_e32 v2, s5
@@ -5894,25 +5852,23 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
-; GFX9-NEXT: s_sub_i32 s10, 0x7f, 64
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
; GFX9-NEXT: s_ashr_i32 s3, s17, 31
-; GFX9-NEXT: s_ashr_i64 s[0:1], s[16:17], s10
-; GFX9-NEXT: s_add_u32 s0, s0, 0
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_and_b32 s2, s2, 1
-; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1]
+; GFX9-NEXT: s_add_u32 s0, s3, 0
+; GFX9-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-NEXT: s_and_b32 s1, s1, 1
+; GFX9-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-NEXT: s_addc_u32 s1, s3, 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_and_b32 s2, s2, 1
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-NEXT: s_addc_u32 s2, s3, 0
-; GFX9-NEXT: s_cselect_b32 s18, 1, 0
-; GFX9-NEXT: s_and_b32 s18, s18, 1
-; GFX9-NEXT: s_brev_b32 s11, 1
-; GFX9-NEXT: s_cmp_lg_u32 s18, 0
+; GFX9-NEXT: s_cselect_b32 s11, 1, 0
+; GFX9-NEXT: s_and_b32 s11, s11, 1
+; GFX9-NEXT: s_brev_b32 s10, 1
+; GFX9-NEXT: s_cmp_lg_u32 s11, 0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT: s_addc_u32 s3, s3, s11
+; GFX9-NEXT: s_addc_u32 s3, s3, s10
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_add_u32 s0, s4, s12
@@ -5959,14 +5915,13 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9-NEXT: s_and_b32 s4, 1, s6
; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX9-NEXT: s_ashr_i32 s7, s3, 31
-; GFX9-NEXT: s_ashr_i64 s[4:5], s[2:3], s10
-; GFX9-NEXT: s_add_u32 s4, s4, 0
-; GFX9-NEXT: s_cselect_b32 s6, 1, 0
-; GFX9-NEXT: s_and_b32 s6, s6, 1
-; GFX9-NEXT: s_cmp_lg_u32 s6, 0
-; GFX9-NEXT: s_addc_u32 s5, s5, 0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
+; GFX9-NEXT: s_add_u32 s4, s7, 0
+; GFX9-NEXT: s_cselect_b32 s5, 1, 0
+; GFX9-NEXT: s_and_b32 s5, s5, 1
+; GFX9-NEXT: s_cmp_lg_u32 s5, 0
+; GFX9-NEXT: s_addc_u32 s5, s7, 0
; GFX9-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-NEXT: s_and_b32 s6, s6, 1
; GFX9-NEXT: s_cmp_lg_u32 s6, 0
@@ -5979,7 +5934,7 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mov_b32_e32 v3, s0
; GFX9-NEXT: v_mov_b32_e32 v8, s1
-; GFX9-NEXT: s_addc_u32 s7, s7, s11
+; GFX9-NEXT: s_addc_u32 s7, s7, s10
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s5
@@ -6029,32 +5984,30 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: s_cselect_b32 s0, 1, 0
-; GFX10-NEXT: s_sub_i32 s10, 0x7f, 64
-; GFX10-NEXT: s_and_b32 s0, 1, s0
; GFX10-NEXT: s_ashr_i32 s3, s17, 31
+; GFX10-NEXT: s_and_b32 s0, 1, s0
+; GFX10-NEXT: s_brev_b32 s10, 1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
-; GFX10-NEXT: s_brev_b32 s11, 1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0
-; GFX10-NEXT: s_ashr_i64 s[0:1], s[16:17], s10
-; GFX10-NEXT: s_add_u32 s0, s0, 0
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_add_u32 s0, s3, 0
+; GFX10-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-NEXT: s_and_b32 s1, s1, 1
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT: s_and_b32 s2, s2, 1
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: v_mov_b32_e32 v1, s8
-; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: s_addc_u32 s1, s1, 0
+; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: s_and_b32 s2, s2, 1
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
; GFX10-NEXT: s_addc_u32 s2, s3, 0
-; GFX10-NEXT: s_cselect_b32 s18, 1, 0
+; GFX10-NEXT: s_cselect_b32 s11, 1, 0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: s_and_b32 s18, s18, 1
-; GFX10-NEXT: s_cmp_lg_u32 s18, 0
-; GFX10-NEXT: s_addc_u32 s3, s3, s11
+; GFX10-NEXT: s_and_b32 s11, s11, 1
+; GFX10-NEXT: s_cmp_lg_u32 s11, 0
+; GFX10-NEXT: s_addc_u32 s3, s3, s10
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo
; GFX10-NEXT: s_add_u32 s0, s4, s12
; GFX10-NEXT: s_cselect_b32 s8, 1, 0
@@ -6088,17 +6041,16 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
; GFX10-NEXT: s_ashr_i32 s5, s9, 31
-; GFX10-NEXT: s_and_b32 s4, 1, s2
; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s3
-; GFX10-NEXT: s_ashr_i64 s[2:3], s[8:9], s10
-; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4
-; GFX10-NEXT: s_add_u32 s2, s2, 0
-; GFX10-NEXT: s_cselect_b32 s6, 1, 0
-; GFX10-NEXT: s_and_b32 s6, s6, 1
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0, s4
-; GFX10-NEXT: s_cmp_lg_u32 s6, 0
-; GFX10-NEXT: s_addc_u32 s3, s3, 0
+; GFX10-NEXT: s_and_b32 s3, 1, s2
+; GFX10-NEXT: s_add_u32 s2, s5, 0
+; GFX10-NEXT: v_cmp_ne_u32_e64 s3, 0, s3
+; GFX10-NEXT: s_cselect_b32 s4, 1, 0
+; GFX10-NEXT: s_and_b32 s4, s4, 1
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0, s3
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
+; GFX10-NEXT: s_addc_u32 s3, s5, 0
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX10-NEXT: s_and_b32 s4, s4, 1
@@ -6111,7 +6063,7 @@ define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX10-NEXT: s_and_b32 s6, s6, 1
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX10-NEXT: s_cmp_lg_u32 s6, 0
-; GFX10-NEXT: s_addc_u32 s1, s5, s11
+; GFX10-NEXT: s_addc_u32 s1, s5, s10
; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, s3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s4, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index bce68f90bc1d9..77ef4c2918e6a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -4781,16 +4781,14 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0
+; GFX6-NEXT: s_ashr_i32 s3, s11, 31
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64
-; GFX6-NEXT: s_ashr_i32 s3, s11, 31
-; GFX6-NEXT: s_ashr_i64 s[0:1], s[10:11], s0
-; GFX6-NEXT: s_add_u32 s0, s0, 0
-; GFX6-NEXT: s_cselect_b32 s2, 1, 0
-; GFX6-NEXT: s_and_b32 s2, s2, 1
-; GFX6-NEXT: s_cmp_lg_u32 s2, 0
-; GFX6-NEXT: s_addc_u32 s1, s1, 0
+; GFX6-NEXT: s_add_u32 s0, s3, 0
+; GFX6-NEXT: s_cselect_b32 s1, 1, 0
+; GFX6-NEXT: s_and_b32 s1, s1, 1
+; GFX6-NEXT: s_cmp_lg_u32 s1, 0
+; GFX6-NEXT: s_addc_u32 s1, s3, 0
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_and_b32 s2, s2, 1
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
@@ -4857,15 +4855,13 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
-; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
-; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64
; GFX8-NEXT: s_ashr_i32 s3, s11, 31
-; GFX8-NEXT: s_ashr_i64 s[0:1], s[10:11], s0
-; GFX8-NEXT: s_add_u32 s0, s0, 0
-; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: s_and_b32 s2, s2, 1
-; GFX8-NEXT: s_cmp_lg_u32 s2, 0
-; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
+; GFX8-NEXT: s_add_u32 s0, s3, 0
+; GFX8-NEXT: s_cselect_b32 s1, 1, 0
+; GFX8-NEXT: s_and_b32 s1, s1, 1
+; GFX8-NEXT: s_cmp_lg_u32 s1, 0
+; GFX8-NEXT: s_addc_u32 s1, s3, 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_and_b32 s2, s2, 1
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
@@ -4931,15 +4927,13 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
-; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
-; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64
; GFX9-NEXT: s_ashr_i32 s3, s11, 31
-; GFX9-NEXT: s_ashr_i64 s[0:1], s[10:11], s0
-; GFX9-NEXT: s_add_u32 s0, s0, 0
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_and_b32 s2, s2, 1
-; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
+; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
+; GFX9-NEXT: s_add_u32 s0, s3, 0
+; GFX9-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-NEXT: s_and_b32 s1, s1, 1
+; GFX9-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-NEXT: s_addc_u32 s1, s3, 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_and_b32 s2, s2, 1
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
@@ -4999,21 +4993,19 @@ define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_ashr_i32 s3, s11, 31
-; GFX10-NEXT: s_and_b32 s2, 1, s1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[6:7], 0
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
-; GFX10-NEXT: s_sub_i32 s0, 0x7f, 64
-; GFX10-NEXT: s_ashr_i64 s[0:1], s[10:11], s0
-; GFX10-NEXT: s_add_u32 s0, s0, 0
-; GFX10-NEXT: s_cselect_b32 s4, 1, 0
+; GFX10-NEXT: s_and_b32 s0, 1, s1
+; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10-NEXT: s_add_u32 s0, s3, 0
+; GFX10-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-NEXT: s_and_b32 s1, s1, 1
; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX10-NEXT: s_and_b32 s4, s4, 1
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, s9
-; GFX10-NEXT: s_cmp_lg_u32 s4, 0
-; GFX10-NEXT: s_addc_u32 s1, s1, 0
+; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: s_and_b32 s2, s2, 1
@@ -5050,7 +5042,6 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v6, v2, vcc
; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc
; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
-; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]
; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
@@ -5061,21 +5052,20 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v7
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX6-NEXT: v_xor_b32_e32 v2, v0, v8
-; GFX6-NEXT: v_ashr_i64 v[0:1], v[6:7], s0
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0, v1
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, v0, v8
; GFX6-NEXT: v_bfrev_b32_e32 v8, 1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; GFX6-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i128_sv:
@@ -5088,7 +5078,6 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v2, vcc
; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
-; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
@@ -5099,21 +5088,20 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v7
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX8-NEXT: v_xor_b32_e32 v2, v0, v8
-; GFX8-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7]
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0, v1
+; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GFX8-NEXT: v_xor_b32_e32 v0, v0, v8
; GFX8-NEXT: v_bfrev_b32_e32 v8, 1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
+; GFX8-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i128_sv:
@@ -5126,7 +5114,6 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v2, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v7, v3, vcc
; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
-; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
@@ -5137,21 +5124,20 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
-; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v7
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-NEXT: v_xor_b32_e32 v2, v0, v8
-; GFX9-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7]
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v8
; GFX9-NEXT: v_bfrev_b32_e32 v8, 1
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0
-; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v3, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v1, v8, vcc
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i128_sv:
@@ -5161,7 +5147,6 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX10-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
-; GFX10-NEXT: s_sub_i32 s0, 0x7f, 64
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
@@ -5172,20 +5157,19 @@ define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX10-NEXT: v_xor_b32_e32 v2, v0, v8
-; GFX10-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7]
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v2
-; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0x80000000, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX10-NEXT: v_xor_b32_e32 v0, v0, v8
+; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v1, 0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v2, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v3, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX10-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
@@ -5209,26 +5193,24 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX6-NEXT: v_bfrev_b32_e32 v8, 1
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
-; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v7
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[2:3], 0
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX6-NEXT: s_sub_i32 s0, 0x7f, 64
-; GFX6-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX6-NEXT: v_ashr_i64 v[0:1], v[6:7], s0
-; GFX6-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0, v1
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i128_vs:
@@ -5251,25 +5233,23 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
-; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v7
+; GFX8-NEXT: v_bfrev_b32_e32 v8, 1
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s4
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX8-NEXT: s_sub_i32 s0, 0x7f, 64
-; GFX8-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX8-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7]
-; GFX8-NEXT: v_bfrev_b32_e32 v8, 1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0, v1
+; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
+; GFX8-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i128_vs:
@@ -5292,25 +5272,23 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
-; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v7
+; GFX9-NEXT: v_bfrev_b32_e32 v8, 1
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s4
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX9-NEXT: s_sub_i32 s0, 0x7f, 64
-; GFX9-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX9-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7]
-; GFX9-NEXT: v_bfrev_b32_e32 v8, 1
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0
-; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v3, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v1, v8, vcc
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i128_vs:
@@ -5331,23 +5309,21 @@ define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX10-NEXT: s_and_b32 s0, 1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
-; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT: s_sub_i32 s0, 0x7f, 64
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
-; GFX10-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX10-NEXT: v_ashrrev_i64 v[0:1], s0, v[6:7]
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v2
-; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0x80000000, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v0, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v2, s0
-; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v3, s0
+; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v7
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v1, 0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v2, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v3, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
; GFX10-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
@@ -5363,13 +5339,11 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX6-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc
; GFX6-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
-; GFX6-NEXT: s_sub_i32 s4, 0x7f, 64
+; GFX6-NEXT: v_bfrev_b32_e32 v20, 1
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
-; GFX6-NEXT: v_bfrev_b32_e32 v20, 1
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
-; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v19
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
@@ -5377,18 +5351,18 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX6-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX6-NEXT: v_ashr_i64 v[0:1], v[18:19], s4
-; GFX6-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc
-; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v20, vcc
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v19
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0, v1
+; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
+; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v1, v20, vcc
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v8, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v9, vcc
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v4, v12
; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc
; GFX6-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc
@@ -5398,7 +5372,6 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
-; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v11
; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
@@ -5406,18 +5379,18 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
-; GFX6-NEXT: v_xor_b32_e32 v6, v5, v4
-; GFX6-NEXT: v_ashr_i64 v[4:5], v[10:11], s4
-; GFX6-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0, v4
-; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GFX6-NEXT: v_addc_u32_e32 v12, vcc, 0, v7, vcc
-; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v20, vcc
-; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
+; GFX6-NEXT: v_xor_b32_e32 v4, v5, v4
+; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v11
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0, v5
+; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
+; GFX6-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc
+; GFX6-NEXT: v_addc_u32_e32 v13, vcc, v5, v20, vcc
+; GFX6-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc
-; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v2i128:
@@ -5428,13 +5401,11 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX8-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc
; GFX8-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
-; GFX8-NEXT: s_sub_i32 s4, 0x7f, 64
+; GFX8-NEXT: v_bfrev_b32_e32 v20, 1
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
-; GFX8-NEXT: v_bfrev_b32_e32 v20, 1
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
-; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v19
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
@@ -5442,18 +5413,18 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX8-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX8-NEXT: v_ashrrev_i64 v[0:1], s4, v[18:19]
-; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0
-; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc
-; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v20, vcc
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v19
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0, v1
+; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
+; GFX8-NEXT: v_addc_u32_e32 v9, vcc, v1, v20, vcc
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v8, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v9, vcc
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v4, v12
; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc
; GFX8-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc
@@ -5463,7 +5434,6 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
-; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v11
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
@@ -5471,18 +5441,18 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
-; GFX8-NEXT: v_xor_b32_e32 v6, v5, v4
-; GFX8-NEXT: v_ashrrev_i64 v[4:5], s4, v[10:11]
-; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0, v4
-; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GFX8-NEXT: v_addc_u32_e32 v12, vcc, 0, v7, vcc
-; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v20, vcc
-; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
+; GFX8-NEXT: v_xor_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v11
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0, v5
+; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
+; GFX8-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc
+; GFX8-NEXT: v_addc_u32_e32 v13, vcc, v5, v20, vcc
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v2i128:
@@ -5493,13 +5463,11 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX9-NEXT: v_subb_co_u32_e32 v18, vcc, v2, v10, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v19, vcc, v3, v11, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
-; GFX9-NEXT: s_sub_i32 s4, 0x7f, 64
+; GFX9-NEXT: v_bfrev_b32_e32 v20, 1
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
-; GFX9-NEXT: v_bfrev_b32_e32 v20, 1
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
-; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v19
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
@@ -5507,18 +5475,18 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX9-NEXT: v_xor_b32_e32 v2, v1, v0
-; GFX9-NEXT: v_ashrrev_i64 v[0:1], s4, v[18:19]
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0
-; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v3, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v20, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v19
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v1, v20, vcc
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v8, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v9, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v4, v12
; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v5, v13, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v6, v14, vcc
@@ -5528,7 +5496,6 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
-; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v11
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
@@ -5536,18 +5503,18 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
-; GFX9-NEXT: v_xor_b32_e32 v6, v5, v4
-; GFX9-NEXT: v_ashrrev_i64 v[4:5], s4, v[10:11]
-; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0, v4
-; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v7, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v20, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
+; GFX9-NEXT: v_xor_b32_e32 v4, v5, v4
+; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v11
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 0, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v5, v20, vcc
+; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v2i128:
@@ -5555,7 +5522,6 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v8
-; GFX10-NEXT: s_sub_i32 s6, 0x7f, 64
; GFX10-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo
@@ -5568,51 +5534,49 @@ define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3]
-; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v19
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v12
; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v10, vcc_lo, v6, v14, vcc_lo
-; GFX10-NEXT: v_xor_b32_e32 v2, v1, v0
+; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[4:5]
-; GFX10-NEXT: v_ashrrev_i64 v[0:1], s6, v[18:19]
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v19
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_cmp_eq_u64_e64 s5, v[10:11], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[10:11], v[6:7]
-; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, 0
-; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v1, 0
+; GFX10-NEXT: v_ashrrev_i32_e32 v7, 31, v11
+; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, 0, v[12:13]
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s4
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[14:15]
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s4
-; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v4, s5
+; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v4, s5
; GFX10-NEXT: v_cmp_eq_u64_e64 s5, 0, v[14:15]
-; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0x80000000, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, v0, s4
-; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, v1, s4
+; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, v3, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, v13, v12, s5
-; GFX10-NEXT: v_xor_b32_e32 v7, v4, v2
-; GFX10-NEXT: v_ashrrev_i64 v[3:4], s6, v[10:11]
+; GFX10-NEXT: v_xor_b32_e32 v4, v4, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, v2, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v5, s4
-; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v11
-; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
-; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, v3, 0
+; GFX10-NEXT: v_and_b32_e32 v3, 1, v4
+; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v7, 0
+; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, 0, v7, vcc_lo
+; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v3
+; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0x80000000, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v19, v6, s4
-; GFX10-NEXT: v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
-; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v7
-; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
-; GFX10-NEXT: v_add_co_ci_u32_e32 v14, vcc_lo, 0x80000000, v5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v12, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v7, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v13, s5
-; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v14, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v5, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v12, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v7, s5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
@@ -5639,34 +5603,32 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: s_subb_u32 s19, s3, s11
; GFX6-NEXT: v_mov_b32_e32 v1, s3
-; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
-; GFX6-NEXT: s_sub_i32 s8, 0x7f, 64
+; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[18:19], v[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0
+; GFX6-NEXT: s_ashr_i32 s3, s19, 31
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; GFX6-NEXT: s_ashr_i32 s3, s19, 31
-; GFX6-NEXT: s_ashr_i64 s[0:1], s[18:19], s8
-; GFX6-NEXT: s_add_u32 s0, s0, 0
-; GFX6-NEXT: s_cselect_b32 s2, 1, 0
-; GFX6-NEXT: s_and_b32 s2, s2, 1
-; GFX6-NEXT: s_cmp_lg_u32 s2, 0
-; GFX6-NEXT: s_addc_u32 s1, s1, 0
+; GFX6-NEXT: s_add_u32 s0, s3, 0
+; GFX6-NEXT: s_cselect_b32 s1, 1, 0
+; GFX6-NEXT: s_and_b32 s1, s1, 1
+; GFX6-NEXT: s_cmp_lg_u32 s1, 0
+; GFX6-NEXT: s_addc_u32 s1, s3, 0
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_and_b32 s2, s2, 1
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
; GFX6-NEXT: s_addc_u32 s2, s3, 0
+; GFX6-NEXT: s_cselect_b32 s9, 1, 0
+; GFX6-NEXT: s_and_b32 s9, s9, 1
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[10:11], 0
-; GFX6-NEXT: s_cselect_b32 s10, 1, 0
-; GFX6-NEXT: s_and_b32 s10, s10, 1
-; GFX6-NEXT: s_brev_b32 s9, 1
-; GFX6-NEXT: s_cmp_lg_u32 s10, 0
+; GFX6-NEXT: s_brev_b32 s8, 1
+; GFX6-NEXT: s_cmp_lg_u32 s9, 0
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX6-NEXT: s_addc_u32 s3, s3, s9
+; GFX6-NEXT: s_addc_u32 s3, s3, s8
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_sub_u32 s0, s4, s12
@@ -5707,29 +5669,28 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0
+; GFX6-NEXT: s_ashr_i32 s7, s3, 31
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
-; GFX6-NEXT: s_ashr_i32 s7, s3, 31
-; GFX6-NEXT: s_ashr_i64 s[4:5], s[2:3], s8
-; GFX6-NEXT: s_add_u32 s4, s4, 0
-; GFX6-NEXT: s_cselect_b32 s6, 1, 0
-; GFX6-NEXT: s_and_b32 s6, s6, 1
-; GFX6-NEXT: s_cmp_lg_u32 s6, 0
-; GFX6-NEXT: s_addc_u32 s5, s5, 0
+; GFX6-NEXT: s_add_u32 s4, s7, 0
+; GFX6-NEXT: s_cselect_b32 s5, 1, 0
+; GFX6-NEXT: s_and_b32 s5, s5, 1
+; GFX6-NEXT: s_cmp_lg_u32 s5, 0
+; GFX6-NEXT: s_addc_u32 s5, s7, 0
; GFX6-NEXT: s_cselect_b32 s6, 1, 0
; GFX6-NEXT: s_and_b32 s6, s6, 1
; GFX6-NEXT: s_cmp_lg_u32 s6, 0
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[14:15], 0
; GFX6-NEXT: s_addc_u32 s6, s7, 0
-; GFX6-NEXT: s_cselect_b32 s8, 1, 0
+; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX6-NEXT: s_and_b32 s8, s8, 1
-; GFX6-NEXT: s_cmp_lg_u32 s8, 0
+; GFX6-NEXT: s_and_b32 s9, s9, 1
+; GFX6-NEXT: s_cmp_lg_u32 s9, 0
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: v_mov_b32_e32 v3, s0
; GFX6-NEXT: v_mov_b32_e32 v8, s1
-; GFX6-NEXT: s_addc_u32 s7, s7, s9
+; GFX6-NEXT: s_addc_u32 s7, s7, s8
; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_mov_b32_e32 v2, s5
@@ -5786,25 +5747,23 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
-; GFX8-NEXT: s_sub_i32 s8, 0x7f, 64
-; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: s_ashr_i32 s3, s19, 31
-; GFX8-NEXT: s_ashr_i64 s[0:1], s[18:19], s8
-; GFX8-NEXT: s_add_u32 s0, s0, 0
-; GFX8-NEXT: s_cselect_b32 s2, 1, 0
-; GFX8-NEXT: s_and_b32 s2, s2, 1
-; GFX8-NEXT: s_cmp_lg_u32 s2, 0
-; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
+; GFX8-NEXT: s_add_u32 s0, s3, 0
+; GFX8-NEXT: s_cselect_b32 s1, 1, 0
+; GFX8-NEXT: s_and_b32 s1, s1, 1
+; GFX8-NEXT: s_cmp_lg_u32 s1, 0
+; GFX8-NEXT: s_addc_u32 s1, s3, 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_and_b32 s2, s2, 1
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
; GFX8-NEXT: s_addc_u32 s2, s3, 0
-; GFX8-NEXT: s_cselect_b32 s10, 1, 0
-; GFX8-NEXT: s_and_b32 s10, s10, 1
-; GFX8-NEXT: s_brev_b32 s9, 1
-; GFX8-NEXT: s_cmp_lg_u32 s10, 0
+; GFX8-NEXT: s_cselect_b32 s9, 1, 0
+; GFX8-NEXT: s_and_b32 s9, s9, 1
+; GFX8-NEXT: s_brev_b32 s8, 1
+; GFX8-NEXT: s_cmp_lg_u32 s9, 0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX8-NEXT: s_addc_u32 s3, s3, s9
+; GFX8-NEXT: s_addc_u32 s3, s3, s8
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: s_sub_u32 s0, s4, s12
@@ -5853,27 +5812,26 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GFX8-NEXT: s_and_b32 s4, 1, s6
-; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: s_ashr_i32 s7, s3, 31
-; GFX8-NEXT: s_ashr_i64 s[4:5], s[2:3], s8
-; GFX8-NEXT: s_add_u32 s4, s4, 0
-; GFX8-NEXT: s_cselect_b32 s6, 1, 0
-; GFX8-NEXT: s_and_b32 s6, s6, 1
-; GFX8-NEXT: s_cmp_lg_u32 s6, 0
-; GFX8-NEXT: s_addc_u32 s5, s5, 0
+; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
+; GFX8-NEXT: s_add_u32 s4, s7, 0
+; GFX8-NEXT: s_cselect_b32 s5, 1, 0
+; GFX8-NEXT: s_and_b32 s5, s5, 1
+; GFX8-NEXT: s_cmp_lg_u32 s5, 0
+; GFX8-NEXT: s_addc_u32 s5, s7, 0
; GFX8-NEXT: s_cselect_b32 s6, 1, 0
; GFX8-NEXT: s_and_b32 s6, s6, 1
; GFX8-NEXT: s_cmp_lg_u32 s6, 0
; GFX8-NEXT: s_addc_u32 s6, s7, 0
-; GFX8-NEXT: s_cselect_b32 s8, 1, 0
+; GFX8-NEXT: s_cselect_b32 s9, 1, 0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX8-NEXT: s_and_b32 s8, s8, 1
-; GFX8-NEXT: s_cmp_lg_u32 s8, 0
+; GFX8-NEXT: s_and_b32 s9, s9, 1
+; GFX8-NEXT: s_cmp_lg_u32 s9, 0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_mov_b32_e32 v3, s0
; GFX8-NEXT: v_mov_b32_e32 v8, s1
-; GFX8-NEXT: s_addc_u32 s7, s7, s9
+; GFX8-NEXT: s_addc_u32 s7, s7, s8
; GFX8-NEXT: v_mov_b32_e32 v1, s4
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_mov_b32_e32 v2, s5
@@ -5930,25 +5888,23 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
-; GFX9-NEXT: s_sub_i32 s8, 0x7f, 64
-; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: s_ashr_i32 s3, s19, 31
-; GFX9-NEXT: s_ashr_i64 s[0:1], s[18:19], s8
-; GFX9-NEXT: s_add_u32 s0, s0, 0
-; GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GFX9-NEXT: s_and_b32 s2, s2, 1
-; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
+; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
+; GFX9-NEXT: s_add_u32 s0, s3, 0
+; GFX9-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-NEXT: s_and_b32 s1, s1, 1
+; GFX9-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-NEXT: s_addc_u32 s1, s3, 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_and_b32 s2, s2, 1
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-NEXT: s_addc_u32 s2, s3, 0
-; GFX9-NEXT: s_cselect_b32 s10, 1, 0
-; GFX9-NEXT: s_and_b32 s10, s10, 1
-; GFX9-NEXT: s_brev_b32 s9, 1
-; GFX9-NEXT: s_cmp_lg_u32 s10, 0
+; GFX9-NEXT: s_cselect_b32 s9, 1, 0
+; GFX9-NEXT: s_and_b32 s9, s9, 1
+; GFX9-NEXT: s_brev_b32 s8, 1
+; GFX9-NEXT: s_cmp_lg_u32 s9, 0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX9-NEXT: s_addc_u32 s3, s3, s9
+; GFX9-NEXT: s_addc_u32 s3, s3, s8
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_sub_u32 s0, s4, s12
@@ -5997,27 +5953,26 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GFX9-NEXT: s_and_b32 s4, 1, s6
-; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: s_ashr_i32 s7, s3, 31
-; GFX9-NEXT: s_ashr_i64 s[4:5], s[2:3], s8
-; GFX9-NEXT: s_add_u32 s4, s4, 0
-; GFX9-NEXT: s_cselect_b32 s6, 1, 0
-; GFX9-NEXT: s_and_b32 s6, s6, 1
-; GFX9-NEXT: s_cmp_lg_u32 s6, 0
-; GFX9-NEXT: s_addc_u32 s5, s5, 0
+; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
+; GFX9-NEXT: s_add_u32 s4, s7, 0
+; GFX9-NEXT: s_cselect_b32 s5, 1, 0
+; GFX9-NEXT: s_and_b32 s5, s5, 1
+; GFX9-NEXT: s_cmp_lg_u32 s5, 0
+; GFX9-NEXT: s_addc_u32 s5, s7, 0
; GFX9-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-NEXT: s_and_b32 s6, s6, 1
; GFX9-NEXT: s_cmp_lg_u32 s6, 0
; GFX9-NEXT: s_addc_u32 s6, s7, 0
-; GFX9-NEXT: s_cselect_b32 s8, 1, 0
+; GFX9-NEXT: s_cselect_b32 s9, 1, 0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX9-NEXT: s_and_b32 s8, s8, 1
-; GFX9-NEXT: s_cmp_lg_u32 s8, 0
+; GFX9-NEXT: s_and_b32 s9, s9, 1
+; GFX9-NEXT: s_cmp_lg_u32 s9, 0
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mov_b32_e32 v3, s0
; GFX9-NEXT: v_mov_b32_e32 v8, s1
-; GFX9-NEXT: s_addc_u32 s7, s7, s9
+; GFX9-NEXT: s_addc_u32 s7, s7, s8
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s5
@@ -6071,30 +6026,28 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[10:11], 0
-; GFX10-NEXT: s_sub_i32 s10, 0x7f, 64
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT: s_brev_b32 s11, 1
+; GFX10-NEXT: s_add_u32 s0, s3, 0
+; GFX10-NEXT: s_brev_b32 s10, 1
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1
-; GFX10-NEXT: s_ashr_i64 s[0:1], s[18:19], s10
-; GFX10-NEXT: s_add_u32 s0, s0, 0
-; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-NEXT: s_and_b32 s1, s1, 1
; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX10-NEXT: s_and_b32 s2, s2, 1
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: v_mov_b32_e32 v2, s17
-; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
-; GFX10-NEXT: s_addc_u32 s1, s1, 0
+; GFX10-NEXT: s_addc_u32 s1, s3, 0
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GFX10-NEXT: v_mov_b32_e32 v1, s16
+; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: s_and_b32 s2, s2, 1
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_mov_b32_e32 v1, s16
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: s_addc_u32 s2, s3, 0
; GFX10-NEXT: s_cselect_b32 s8, 1, 0
-; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: s_and_b32 s8, s8, 1
+; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: s_cmp_lg_u32 s8, 0
-; GFX10-NEXT: s_addc_u32 s3, s3, s11
+; GFX10-NEXT: s_addc_u32 s3, s3, s10
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo
; GFX10-NEXT: s_sub_u32 s0, s4, s12
; GFX10-NEXT: s_cselect_b32 s8, 1, 0
@@ -6127,20 +6080,19 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
; GFX10-NEXT: s_ashr_i32 s5, s9, 31
-; GFX10-NEXT: s_and_b32 s4, 1, s2
; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s3
; GFX10-NEXT: v_cmp_gt_i64_e64 s3, s[14:15], 0
-; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s3
-; GFX10-NEXT: s_ashr_i64 s[2:3], s[8:9], s10
-; GFX10-NEXT: s_add_u32 s2, s2, 0
-; GFX10-NEXT: s_cselect_b32 s6, 1, 0
+; GFX10-NEXT: s_and_b32 s3, 1, s2
+; GFX10-NEXT: s_add_u32 s2, s5, 0
+; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
+; GFX10-NEXT: s_cselect_b32 s4, 1, 0
+; GFX10-NEXT: s_and_b32 s4, s4, 1
; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
-; GFX10-NEXT: s_and_b32 s6, s6, 1
+; GFX10-NEXT: s_cmp_lg_u32 s4, 0
; GFX10-NEXT: v_mov_b32_e32 v6, s1
-; GFX10-NEXT: s_cmp_lg_u32 s6, 0
-; GFX10-NEXT: s_addc_u32 s3, s3, 0
+; GFX10-NEXT: s_addc_u32 s3, s5, 0
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX10-NEXT: s_and_b32 s4, s4, 1
@@ -6153,7 +6105,7 @@ define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128>
; GFX10-NEXT: s_and_b32 s6, s6, 1
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
; GFX10-NEXT: s_cmp_lg_u32 s6, 0
-; GFX10-NEXT: s_addc_u32 s1, s5, s11
+; GFX10-NEXT: s_addc_u32 s1, s5, s10
; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, s3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s4, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
index 5feb071f7f830..66628a115253a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
@@ -251,42 +251,45 @@ define <2 x i32> @v_udiv_v2i32_pow2k_denom(<2 x i32> %num) {
; GISEL-LABEL: v_udiv_v2i32_pow2k_denom:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_movk_i32 s8, 0x1000
-; GISEL-NEXT: v_cvt_f32_u32_e32 v2, s8
-; GISEL-NEXT: s_sub_i32 s4, 0, s8
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GISEL-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v2
-; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GISEL-NEXT: v_mul_lo_u32 v4, s4, v3
-; GISEL-NEXT: v_mul_lo_u32 v5, s4, v2
-; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT: v_mul_hi_u32 v5, v2, v5
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v4
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GISEL-NEXT: v_mul_hi_u32 v3, v0, v3
-; GISEL-NEXT: v_mul_hi_u32 v2, v1, v2
-; GISEL-NEXT: v_lshlrev_b32_e32 v4, 12, v3
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v3
-; GISEL-NEXT: v_lshlrev_b32_e32 v6, 12, v2
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v2
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
-; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
-; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
-; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GISEL-NEXT: v_subrev_i32_e64 v4, s[4:5], s8, v0
-; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v7, s[4:5]
-; GISEL-NEXT: v_subrev_i32_e64 v5, s[6:7], s8, v1
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, 1, v3
-; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5]
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v2
-; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
+; GISEL-NEXT: s_movk_i32 s4, 0x1000
+; GISEL-NEXT: v_mov_b32_e32 v2, 0x1000
+; GISEL-NEXT: v_mov_b32_e32 v3, 0xfffff000
+; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s4
+; GISEL-NEXT: v_cvt_f32_u32_e32 v5, v2
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; GISEL-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
+; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GISEL-NEXT: v_mul_lo_u32 v6, v3, v4
+; GISEL-NEXT: v_mul_lo_u32 v3, v3, v5
+; GISEL-NEXT: v_mul_hi_u32 v6, v4, v6
+; GISEL-NEXT: v_mul_hi_u32 v3, v5, v3
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, v5, v3
+; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4
+; GISEL-NEXT: v_mul_hi_u32 v3, v1, v3
+; GISEL-NEXT: v_lshlrev_b32_e32 v5, 12, v4
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4
+; GISEL-NEXT: v_lshlrev_b32_e32 v7, 12, v3
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v3
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
+; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
+; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GISEL-NEXT: v_subrev_i32_e64 v5, s[4:5], s4, v0
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v2
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5]
+; GISEL-NEXT: v_sub_i32_e64 v6, s[6:7], v1, v2
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5]
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v3
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_udiv_v2i32_pow2k_denom:
@@ -371,41 +374,44 @@ define <2 x i32> @v_udiv_v2i32_oddk_denom(<2 x i32> %num) {
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b32 s8, 0x12d8fb
-; GISEL-NEXT: v_cvt_f32_u32_e32 v2, s8
-; GISEL-NEXT: s_sub_i32 s4, 0, s8
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GISEL-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v2
-; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GISEL-NEXT: v_mul_lo_u32 v4, s4, v3
-; GISEL-NEXT: v_mul_lo_u32 v5, s4, v2
-; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT: v_mul_hi_u32 v5, v2, v5
-; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v4
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GISEL-NEXT: v_mul_hi_u32 v3, v0, v3
-; GISEL-NEXT: v_mul_hi_u32 v2, v1, v2
-; GISEL-NEXT: v_mul_lo_u32 v4, v3, s8
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v3
-; GISEL-NEXT: v_mul_lo_u32 v6, v2, s8
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v2
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
-; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
+; GISEL-NEXT: v_mov_b32_e32 v2, 0x12d8fb
+; GISEL-NEXT: v_mov_b32_e32 v3, 0xffed2705
+; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s8
+; GISEL-NEXT: v_cvt_f32_u32_e32 v5, v2
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; GISEL-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
+; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GISEL-NEXT: v_mul_lo_u32 v6, v3, v4
+; GISEL-NEXT: v_mul_lo_u32 v3, v3, v5
+; GISEL-NEXT: v_mul_hi_u32 v6, v4, v6
+; GISEL-NEXT: v_mul_hi_u32 v3, v5, v3
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, v5, v3
+; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4
+; GISEL-NEXT: v_mul_hi_u32 v3, v1, v3
+; GISEL-NEXT: v_mul_lo_u32 v5, v4, s8
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4
+; GISEL-NEXT: v_mul_lo_u32 v7, v3, v2
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v3
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
+; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v7
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
-; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GISEL-NEXT: v_subrev_i32_e64 v4, s[4:5], s8, v0
-; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v7, s[4:5]
-; GISEL-NEXT: v_subrev_i32_e64 v5, s[6:7], s8, v1
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, 1, v3
-; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5]
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v2
+; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GISEL-NEXT: v_subrev_i32_e64 v5, s[4:5], s8, v0
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v2
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5]
+; GISEL-NEXT: v_sub_i32_e64 v6, s[6:7], v1, v2
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5]
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v3
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_udiv_v2i32_oddk_denom:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
index f3dc84b12c5ec..56d2311f50aa8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
@@ -214,21 +214,13 @@ define i32 @v_urem_i32_pow2k_denom(i32 %num) {
}
define <2 x i32> @v_urem_v2i32_pow2k_denom(<2 x i32> %num) {
-; GISEL-LABEL: v_urem_v2i32_pow2k_denom:
-; GISEL: ; %bb.0:
-; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_add_i32 s4, 0x1000, -1
-; GISEL-NEXT: v_and_b32_e32 v0, s4, v0
-; GISEL-NEXT: v_and_b32_e32 v1, s4, v1
-; GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; CGP-LABEL: v_urem_v2i32_pow2k_denom:
-; CGP: ; %bb.0:
-; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_movk_i32 s4, 0xfff
-; CGP-NEXT: v_and_b32_e32 v0, s4, v0
-; CGP-NEXT: v_and_b32_e32 v1, s4, v1
-; CGP-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: v_urem_v2i32_pow2k_denom:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_movk_i32 s4, 0xfff
+; CHECK-NEXT: v_and_b32_e32 v0, s4, v0
+; CHECK-NEXT: v_and_b32_e32 v1, s4, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = urem <2 x i32> %num, <i32 4096, i32 4096>
ret <2 x i32> %result
}
@@ -265,32 +257,33 @@ define <2 x i32> @v_urem_v2i32_oddk_denom(<2 x i32> %num) {
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b32 s4, 0x12d8fb
-; GISEL-NEXT: v_cvt_f32_u32_e32 v2, s4
-; GISEL-NEXT: s_sub_i32 s5, 0, s4
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GISEL-NEXT: v_mul_lo_u32 v3, s5, v2
-; GISEL-NEXT: v_mul_hi_u32 v3, v2, v3
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GISEL-NEXT: v_mul_hi_u32 v3, v0, v2
-; GISEL-NEXT: v_mul_hi_u32 v2, v1, v2
-; GISEL-NEXT: v_mul_lo_u32 v3, v3, s4
-; GISEL-NEXT: v_mul_lo_u32 v2, v2, s4
-; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
-; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
-; GISEL-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
-; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v1
+; GISEL-NEXT: v_mov_b32_e32 v2, 0x12d8fb
+; GISEL-NEXT: v_mov_b32_e32 v3, 0xffed2705
+; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s4
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GISEL-NEXT: v_mul_lo_u32 v3, v3, v4
+; GISEL-NEXT: v_mul_hi_u32 v3, v4, v3
+; GISEL-NEXT: v_add_i32_e32 v3, vcc, v4, v3
+; GISEL-NEXT: v_mul_hi_u32 v4, v0, v3
+; GISEL-NEXT: v_mul_hi_u32 v3, v1, v3
+; GISEL-NEXT: v_mul_lo_u32 v4, v4, s4
+; GISEL-NEXT: v_mul_lo_u32 v3, v3, v2
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
+; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
+; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
+; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v1, v2
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GISEL-NEXT: v_subrev_i32_e32 v2, vcc, s4, v0
-; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v1
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GISEL-NEXT: v_subrev_i32_e32 v3, vcc, s4, v0
+; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v1, v2
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_urem_v2i32_oddk_denom:
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