[llvm] 64a1581 - [PowerPC]Add addex instruction definition and MC tests

[Lei Huang via llvm-commits]

Author: Lei Huang
Date: 2021-07-26T14:55:38-05:00
New Revision: 64a15817a01703ea2206dd02f27a166ea1890ecb

URL: https://github.com/llvm/llvm-project/commit/64a15817a01703ea2206dd02f27a166ea1890ecb
DIFF: https://github.com/llvm/llvm-project/commit/64a15817a01703ea2206dd02f27a166ea1890ecb.diff

LOG: [PowerPC]Add addex instruction definition and MC tests

Add td definitions and asm/disasm tests for the addex instruction introduced in
ISA 3.0.

Reviewed By: nemanjai, amyk, NeHuang

Differential Revision: https://reviews.llvm.org/D106666

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/P9InstrResources.td
    llvm/lib/Target/PowerPC/PPCInstrFormats.td
    llvm/lib/Target/PowerPC/PPCInstrInfo.td
    llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
    llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
    llvm/test/MC/PowerPC/ppc64-encoding.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td
index 04777bacca455..76663acf47829 100644
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1429,5 +1429,6 @@ def : InstRW<[],
   DCBA,
   DCBI,
   DCCCI,
-  ICCCI
+  ICCCI,
+  ADDEX
 )> { let Unsupported = 1; }

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index cab5774244016..91b507ea6c4cc 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -2141,6 +2141,24 @@ class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
   let Inst{31}    = RC;
 }
 
+class Z23Form_RTAB5_CY2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+                        string asmstr, InstrItinClass itin, list<dag> pattern>
+         : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<5> RT;
+  bits<5> RA;
+  bits<5> RB;
+  bits<2> CY;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RT;
+  let Inst{11-15} = RA;
+  let Inst{16-20} = RB;
+  let Inst{21-22} = CY;
+  let Inst{23-30} = xo;
+  let Inst{31} = 0;
+}
+
 //===----------------------------------------------------------------------===//
 // EmitTimePseudo won't have encoding information for the [MC]CodeEmitter
 // stuff

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index edcf1b9001626..05924209f5143 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3155,6 +3155,10 @@ def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
 def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
                         "moduw $rT, $rA, $rB", IIC_IntDivW,
                         [(set i32:$rT, (urem i32:$rA, i32:$rB))]>;
+let hasSideEffects = 1 in
+def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$rT),
+                              (ins gprc:$rA, gprc:$rB, u2imm:$CY),
+                              "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, []>;
 }
 
 let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.

diff  --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
index 7242f05e0febf..e0e1b6c826cd7 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
@@ -484,6 +484,9 @@
 # CHECK: modsw 2, 3, 4
 0x7c 0x43 0x26 0x16
 
+# CHECK: addex 2, 4, 5, 0
+0x7C 0x44 0x29 0x54
+
 # CHECK: moduw 2, 3, 4
 0x7c 0x43 0x22 0x16
 

diff  --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
index 4f41bf78d4a8e..f005b252c1dc8 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
@@ -448,6 +448,9 @@
 # CHECK: modsw 2, 3, 4
 0x16 0x26 0x43 0x7c
 
+# CHECK: addex 2, 4, 5, 0
+0x54 0x29 0x44 0x7C
+
 # CHECK: moduw 2, 3, 4
 0x16 0x22 0x43 0x7c
 

diff  --git a/llvm/test/MC/PowerPC/ppc64-encoding.s b/llvm/test/MC/PowerPC/ppc64-encoding.s
index 48972c1787adb..3f104cd16d9b5 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding.s
@@ -416,6 +416,9 @@
 # CHECK-BE: addeo. 2, 3, 4                  # encoding: [0x7c,0x43,0x25,0x15]
 # CHECK-LE: addeo. 2, 3, 4                  # encoding: [0x15,0x25,0x43,0x7c]
             addeo. 2, 3, 4
+# CHECK-BE: addex 2, 4, 5, 0                # encoding: [0x7c,0x44,0x29,0x54]
+# CHECK-LE: addex 2, 4, 5, 0                # encoding: [0x54,0x29,0x44,0x7c]
+            addex 2, 4, 5, 0
 # CHECK-BE: subfe 2, 3, 4                   # encoding: [0x7c,0x43,0x21,0x10]
 # CHECK-LE: subfe 2, 3, 4                   # encoding: [0x10,0x21,0x43,0x7c]
             subfe 2, 3, 4