[PATCH] D106603: [PowerPC] Add implicit-def RM to instructions mtfsb[01]
Lei Huang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 26 12:07:14 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2d788959edda: [PowerPC] Add implicit-def RM to instructions mtfsb[01] (authored by lei).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106603/new/
https://reviews.llvm.org/D106603
Files:
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
Index: llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
+++ llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
@@ -272,15 +272,15 @@
; CHECK-NEXT: mffs 0
; CHECK-NEXT: mtfsb1 31
; CHECK-NEXT: lis 3, .LCPI0_0 at ha
-; CHECK-NEXT: lfs 2, .LCPI0_0 at l(3)
+; CHECK-NEXT: lfs 1, .LCPI0_0 at l(3)
; CHECK-NEXT: mtfsb0 30
; CHECK-NEXT: lis 3, .LCPI0_1 at ha
-; CHECK-NEXT: fadd 1, 30, 31
+; CHECK-NEXT: fadd 2, 30, 31
; CHECK-NEXT: mtfsf 1, 0
; CHECK-NEXT: lfs 0, .LCPI0_1 at l(3)
-; CHECK-NEXT: fctiwz 1, 1
-; CHECK-NEXT: stfd 1, 88(1)
-; CHECK-NEXT: fcmpu 0, 30, 2
+; CHECK-NEXT: fctiwz 2, 2
+; CHECK-NEXT: stfd 2, 88(1)
+; CHECK-NEXT: fcmpu 0, 30, 1
; CHECK-NEXT: lwz 3, 100(1)
; CHECK-NEXT: fcmpu 1, 31, 0
; CHECK-NEXT: lwz 4, 92(1)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3089,7 +3089,7 @@
// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def
// RM should be set.
-let hasSideEffects = 1 in {
+let hasSideEffects = 1, Defs = [RM] in {
def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
"mtfsb0 $FM", IIC_IntMTFSB0,
[(int_ppc_mtfsb0 timm:$FM)]>,
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