[PATCH] D103955: [MCA] Use LSU for the in-order pipeline

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic updated this revision to Diff 361740.
asavonic added a comment.

- Rebased the patch and fixed CR comments.

Note that stores retire out-of-order on Cortex-A55 after D105541 <https://reviews.llvm.org/D105541>.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103955/new/

https://reviews.llvm.org/D103955

Files:
  llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
  llvm/lib/MCA/Context.cpp
  llvm/lib/MCA/Stages/InOrderIssueStage.cpp
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-noalias.s

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