[PATCH] D106649: [RISCV] Add tests showing missed vector saturating add/sub combines

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM



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Comment at: llvm/test/CodeGen/RISCV/rvv/combine-sats.ll:83
+; RV32-NEXT:    vsub.vv v25, v8, v9
+; RV32-NEXT:    vmsltu.vv v0, v8, v25
+; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
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I assume this gets expanded because the legalizer is looking for UMIN/UMAX to be Legal rather than Custom?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D106649/new/

https://reviews.llvm.org/D106649